PIC16F716-I-P Datasheet, PDF (80/136 Pages) Microchip Technology – 8-bit Flash-based Microcontroller with A/D Converter and Enhanced Capture/Compare/PWM

PIC16F716
TABLE 10-2: PIC16F716 INSTRUCTION SET
Mnemonic,
Operands
Description
14-Bit Opcode
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d Add W and f
f, d AND W with f
f
Clear f
–
Clear W
f, d Complement f
f, d Decrement f
f, d Decrement f, Skip if 0
f, d Increment f
f, d Increment f, Skip if 0
f, d Inclusive OR W with f
f, d Move f
f
Move W to f
–
No Operation
f, d Rotate Left f through Carry
f, d Rotate Right f through Carry
f, d Subtract W from f
f, d Swap nibbles in f
f, d Exclusive OR W with f
1
00 0111 dfff ffff C, DC, Z 1, 2
1
00 0101 dfff ffff
Z
1, 2
1
00 0001 lfff ffff
Z
2
1
00 0001 0xxx xxxx
Z
1
00 1001 dfff ffff
Z
1, 2
1
00 0011 dfff ffff
Z
1, 2
1(2) 00 1011 dfff ffff
1, 2, 3
1
00 1010 dfff ffff
Z
1, 2
1(2) 00 1111 dfff ffff
1, 2, 3
1
00 0100 dfff ffff
Z
1, 2
1
00 1000 dfff ffff
Z
1, 2
1
00 0000 lfff ffff
1
00 0000 0xx0 0000
1
00 1101 dfff ffff
C
1, 2
1
00 1100 dfff ffff
C
1, 2
1
00 0010 dfff ffff C, DC, Z 1, 2
1
00 1110 dfff ffff
1, 2
1
00 0110 dfff ffff
Z
1, 2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Note 1:
2:
3:
f, b Bit Clear f
f, b Bit Set f
f, b Bit Test f, Skip if Clear
f, b Bit Test f, Skip if Set
1
01 00bb bfff ffff
1, 2
1
01 01bb bfff ffff
1, 2
1 (2) 01 10bb bfff ffff
3
1 (2) 01 11bb bfff ffff
3
LITERAL AND CONTROL OPERATIONS
k
Add literal and W
k
AND literal with W
k
Call Subroutine
–
Clear Watchdog Timer
k
Go to address
k
Inclusive OR literal with W
k
Move literal to W
–
Return from interrupt
k
Return with literal in W
–
Return from Subroutine
–
Go into Standby mode
k
Subtract W from literal
k
Exclusive OR literal with W
1
11 111x kkkk kkkk C, DC, Z
1
11 1001 kkkk kkkk
Z
2
10 0kkk kkkk kkkk
1
00 0000 0110 0100 TO, PD
2
10 1kkk kkkk kkkk
1
11 1000 kkkk kkkk
Z
1
11 00xx kkkk kkkk
2
00 0000 0000 1001
2
11 01xx kkkk kkkk
2
00 0000 0000 1000
1
00 0000 0110 0011 TO, PD
1
11 110x kkkk kkkk C, DC, Z
1
11 1010 kkkk kkkk
Z
When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second
cycle is executed as a NOP.
DS41206B-page 78
© 2007 Microchip Technology Inc.