PIC16F716-I-P Datasheet, PDF(11/136 Page) Microchip Technology – 8-bit Flash-based Microcontroller with A/D Converter and Enhanced Capture/Compare/PWM

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PIC16F716-I-P Datasheet, PDF (11/136 Pages) Microchip Technology – 8-bit Flash-based Microcontroller with A/D Converter and Enhanced Capture/Compare/PWM

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PIC16F716

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral modules for controlling the

desired operation of the device. These registers are

implemented as static RAM. A list of these registers is

give in Table 2-1.

The Special Function Registers can be classified into

two sets; core (CPU) and peripheral. Those registers

associated with the core functions are described in

detail in this section. Those related to the operation of

the peripheral features are described in detail in that

peripheral feature section.

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY BANK 0

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Page

00h

INDF(1)

Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000 18

01h

TMR0

Timer0 moduleâs register

02h

PCL(1)

Program Counterâs (PC) Least Significant Byte

xxxx xxxx 27

0000 0000 17

03h

STATUS(1)

IRP(4)

RP1(4)

RP0

TO

PD

Z

DC

C

0001 1xxx 11

04h

FSR(1)

Indirect Data Memory Address Pointer

xxxx xxxx 18

05h

PORTA(5,6)

â

â

â(7)

RA4

RA3

RA2

RA1

RA0

---x 0000 19

06h

PORTB(5,6)

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

xxxx xxxx 21

07h-09h

0Ah

0Bh

â

PCLATH(1,2)

INTCON(1)

Unimplemented

â

â

GIE

PEIE

â

T0IE

Write Buffer for the upper 5 bits of the Program Counter

INTE

RBIE

T0IF

INTF

RBIF

â

---0 0000 17

0000 000x 13

0Ch

PIR1

â

ADIF

â

â

â

CCP1IF TMR2IF TMR1IF -0-- -000 15

0Dh

â

Unimplemented

â

0Eh

TMR1L

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

xxxx xxxx 29

0Fh

TMR1H

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

xxxx xxxx 29

10h

T1CON

â

â

T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 32

11h

TMR2

Timer2 Moduleâs Register

0000 0000 35

12h

T2CON

â

TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 36

13h-14h

â

Unimplemented

â

15h

CCPR1L

Capture/Compare/PWM Register 1 (LSB)

xxxx xxxx 48

16h

CCPR1H Capture/Compare/PWM Register 1 (MSB)

xxxx xxxx 48

17h

CCP1CON

P1M1

P1M0

DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 48

18h

PWM1CON PRSEN

PDC6

PDC5

PDC4

PDC3

PDC2

PDC1

PDC0 0000 0000 60

19h

ECCPAS

ECCPASE ECCPAS2 â(8) ECCPAS0 PSSAC1 PSSAC0 PSSBD1 PSSBD0 00-0 0000 57

1Ah-1Dh

â

Unimplemented

â

1Eh

ADRES

A/D Result Register

xxxx xxxx 37

1Fh

ADCON0

ADCS1 ADCS0

CHS2

CHS1

CHS0 GO/DONE â(7)

ADON 0000 0000 41

Legend:

Note 1:

2:

3:

4:

5:

6:

7:

8:

x = unknown, u = unchanged, q = value depends on condition, â = unimplemented, read as â0â, Shaded locations are unimplemented,

read as â0â.

These registers can be addressed from either bank.

The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are

transferred to the upper byte of the program counter.

Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.

The IRP and RP1 bits are reserved. Always maintain these bits clear.

On any device Reset, these pins are configured as inputs.

This is the value that will be in the PORT output latch.

Reserved bits, do not use.

ECCPAS1 bit is not used on PIC16F716.

Â© 2007 Microchip Technology Inc.

DS41206B-page 9

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