PIC16F716-I-P Datasheet, PDF (21/136 Pages) Microchip Technology – 8-bit Flash-based Microcontroller with A/D Converter and Enhanced Capture/Compare/PWM

3.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
3.1 PORTA and the TRISA Register
PORTA is a 5-bit wide bidirectional port. The
corresponding data direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a High-impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the PORT latch.
All write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the
PORT data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
PORTA pins, RA<3:0>, are multiplexed with analog
inputs and analog VREF input. The operation of each
pin is selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register 1).
Note:
On a Power-on Reset, these pins are
configured as analog inputs and read as
‘0’.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Note:
Setting RA3:0 to output while in Analog
mode will force pins to output contents of
data latch.
PIC16F716
EXAMPLE 3-1: INITIALIZING PORTA
BCF STATUS, RP0
CLRF PORTA
BSF STATUS, RP0
MOVLW 0xEF
MOVWF TRISA
BCF STATUS, RP0
;
;Initialize PORTA by
;clearing output
;data latches
;Select Bank 1
;Value used to
;initialize data
;direction
;Set RA<3:0> as inputs
;RA<4> as outputs
;Return to Bank 0
FIGURE 3-1:
BLOCK DIAGRAM OF
RA<3:0>
DATA
BUS
WR
PORT
D
Q
CK _Q
Data Latch
D
Q
VDD
P
VDD
N
I/O pin
WR
TRIS
CK _Q
TRIS Latch
VSS VSS
Analog
Input
mode
RD TRIS
Q
D
TTL
Input
Buffer
EN
RD PORT
To A/D Converter
© 2007 Microchip Technology Inc.
DS41206B-page 19