PIC16F716-I-P Datasheet, PDF (12/136 Pages) Microchip Technology – 8-bit Flash-based Microcontroller with A/D Converter and Enhanced Capture/Compare/PWM

PIC16F716
TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY BANK 1
Address
Name
80h
INDF⁽¹⁾
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000
81h
82h
83h
84h
85h
86h
87h-89h
8Ah
8Bh
8Ch
8Dh
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0
PCL⁽¹⁾
Program Counter’s (PC) Least Significant Byte
STATUS⁽¹⁾
FSR⁽¹⁾
TRISA
IRP⁽⁴⁾
RP1⁽⁴⁾
RP0
TO
Indirect Data Memory Address Pointer
—
—
—⁽⁷⁾ TRISA4
PD
Z
DC
C
TRISA3 TRISA2 TRISA1 TRISA0
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
—
PCLATH^(1,2)
INTCON⁽¹⁾
Unimplemented
—
—
GIE
PEIE
—
T0IE
Write Buffer for the upper 5 bits of the Program Counter
INTE
RBIE
T0IF
INTF
RBIF
PIE1
—
ADIE
—
—
—
CCP1IE TMR2IE TMR1IE
—
Unimplemented
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
---1 1111
1111 1111
—
---0 0000
0000 000x
-0-- -000
—
Page
18
12
17
11
18
19
21
17
13
14
8Eh
PCON
—
—
—
—
—
—
POR
BOR ---- --qq 16
8Fh-91h
—
Unimplemented
—
92h
PR2
Timer2 Period Register
1111 1111 35, 52
93h-9Eh
—
Unimplemented
—
9Fh
ADCON1
—
—
—
—
—
PCFG2 PCFG1 PCFG0 ---- -000 42
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, Shaded locations are unimplemented,
read as ‘0’.
These registers can be addressed from either bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are
transferred to the upper byte of the program counter.
Other (non Power-up) Resets include: external Reset through MCLR and the Watchdog Timer Reset.
The IRP and RP1 bits are reserved. Always maintain these bits clear.
On any device Reset, these pins are configured as inputs.
This is the value that will be in the PORT output latch.
Reserved bits, do not use.
DS41206B-page 10
© 2007 Microchip Technology Inc.