PIC16F628-20P Datasheet, PDF (63/170 Pages) Microchip Technology – FLASH-Based 8-Bit CMOS Microcontroller

PIC16F62X
11.0 CAPTURE/COMPARE/PWM
(CCP) MODULE
The CCP (Capture/Compare/PWM) module contains a
16-bit register which can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM
master/slave Duty Cycle register. Table 11-1 shows the
timer resources of the CCP Module modes.
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Additional information on the CCP module is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
TABLE 11-1: CCP MODE - TIMER
RESOURCE
CCP Mode
Capture
Compare
PWM
Timer Resource
Timer1
Timer1
Timer2
REGISTER 11-1:
CCP1CON REGISTER (ADDRESS: 17h)
U-0
U-0
R/W-0 R/W-0
—
—
CCP1X CCP1Y
bit 7
R/W-0
CCP1M3
R/W-0 R/W-0 R/W-0
CCP1M2 CCP1M1 CCP1M0
bit 0
bit 7-6
bit 5-4
bit 3-0
Unimplemented: Read as '0'
CCP1X:CCP1Y: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in
CCPRxL.
CCP1M3:CCP1M0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1
11xx = PWM mode
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
 2003 Microchip Technology Inc.
Preliminary
DS40300C-page 61