PIC16F628-20P Datasheet, PDF (107/170 Pages) Microchip Technology – FLASH-Based 8-Bit CMOS Microcontroller

PIC16F62X
14.9.1 WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1. External RESET input on MCLR pin
2. Watchdog Timer Wake-up (if WDT was enabled)
3. Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
The first event will cause a device RESET. The two
latter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
PD bit, which is set on power-up is cleared when
SLEEP is invoked. TO bit is cleared if WDT Wake-up
occurred.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the
corresponding interrupt enable bit must be set
(enabled). Wake-up is regardless of the state of the
GIE bit. If the GIE bit is clear (disabled), the device con-
tinues execution at the instruction after the SLEEP
instruction. If the GIE bit is set (enabled), the device
executes the instruction after the SLEEP instruction
and then branches to the interrupt address (0004h). In
cases where the execution of the instruction following
SLEEP is not desirable, the user should have an NOP
after the SLEEP instruction.
Note:
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP instruction is completely executed.
The WDT is cleared when the device wakes-up from
SLEEP, regardless of the source of wake-up.
FIGURE 14-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC1
CLKOUT⁽⁴⁾
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Tost⁽²⁾
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
Instruction
Fetched
Instruction
Executed
Inst(PC) = SLEEP
Inst(PC - 1)
PC+1
Inst(PC + 1)
SLEEP
PC+2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt Latency
(Note 2)
PC+2
Inst(PC + 2)
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
Inst(0004h)
Dummy cycle
0005h
Inst(0005h)
Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.
2: TOST = 1024TOSC (drawing not to scale). Approximately 1 µs delay will be there for ER Osc mode.
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue
in-line.
4: CLKOUT is not available in these Osc modes, but shown here for timing reference.
14.10 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
Note:
The entire data EEPROM and FLASH
program memory will be erased when the
code protection is turned off. The INTRC
calibration data is not erased.
14.11 User ID Locations
Four memory locations (2000h-2003h) are designated
as user ID locations where the user can store
checksum or other code-identification numbers. These
locations are not accessible during normal execution
but are readable and writable during program/verify.
Only the Least Significant 4 bits of the user ID locations
are used.
 2003 Microchip Technology Inc.
Preliminary
DS40300C-page 105