PIC16F72-E Datasheet, PDF (59/136 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH Microcontoller with A/D Converter

10.5 A/D Operation During SLEEP
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared,
and the result loaded into the ADRES register. If the
A/D interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
Note:
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, ensure the SLEEP
instruction immediately follows the
instruction that sets the GO/DONE bit.
PIC16F72
10.6 Effects of a RESET
A device RESET forces all registers to their RESET
state. The A/D module is disabled and any conversion
in progress is aborted. All A/D input pins are configured
as analog inputs.
The ADRES register will contain unknown data after a
Power-on Reset.
10.7 Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP1 module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-
grammed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the ADRES to
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
done before the “special event trigger” sets the
GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH A/D
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
0Bh,8Bh ^{INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x}
10Bh,18Bh
0Ch
PIR1
—
ADIF
—
— SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000
8Ch
PIE1
—
ADIE
—
— SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000
1Eh
ADRES A/D Result Register
xxxx xxxx
1Fh
ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0
9Fh
ADCON1 —
—
—
—
— PCFG2 PCFG1 PCFG0 ---- -000
0000 000u
-0-- 0000
-0-- 0000
uuuu uuuu
0000 00-0
---- -000
05h
PORTA
—
—
RA5 RA4 RA3
RA2
RA1
RA0 ^{--0x 0000 --0u 0000}
85h
TRISA
—
— PORTA Data Direction Register
--11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
© 2007 Microchip Technology Inc.
DS39597C-page 57