PIC16F72-E Datasheet, PDF (53/136 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH Microcontoller with A/D Converter

PIC16F72
9.3.2 MASTER MODE OPERATION
Master mode operation is supported in firmware using
interrupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits
are cleared from a RESET or when the SSP module is
disabled. The STOP (P) and START (S) bits will toggle,
based on the START and STOP conditions. Control of
the I²C bus may be taken when the P bit is set, or the
bus is IDLE and both the S and P bits are clear.
In Master mode operation, the SCL and SDA lines are
manipulated in firmware by clearing the corresponding
TRISC<4:3> bit(s). The output level is always low, irre-
spective of the value(s) in PORTC<4:3>. So, when
transmitting data, a ‘1’ data bit must have the
TRISC<4> bit set (input) and a ‘0’ data bit must have
the TRISC<4> bit cleared (output). The same scenario
is true for the SCL line with the TRISC<3> bit.
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
Master mode operation can be done with either the
Slave mode IDLE (SSPM3:SSPM0 = 1011), or with the
Slave mode active. When both Master mode operation
and Slave modes are used, the software needs to
differentiate the source(s) of the interrupt.
For more information on Master mode operation, see
AN554 - Software Implementation of I²C Bus Master.
9.3.3 MULTI-MASTER MODE OPERATION
In Multi-Master mode operation, the interrupt genera-
tion on the detection of the START and STOP condi-
tions allows the determination of when the bus is free.
The STOP (P) and START (S) bits are cleared from a
RESET or when the SSP module is disabled. The
STOP (P) and START (S) bits will toggle, based on the
START and STOP conditions. Control of the I²C bus
may be taken when bit P (SSPSTAT<4>) is set, or the
bus is IDLE and both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the STOP condition occurs.
In Multi-Master mode operation, the SDA line must be
monitored to see if the signal level is the expected out-
put level. This check only needs to be done when a
high level is output. If a high level is expected and a low
level is present, the device needs to release the SDA
and SCL lines (set TRISC<4:3>). There are two stages
where this arbitration can be lost:
• Address Transfer
• Data Transfer
When the slave logic is enabled, the Slave device con-
tinues to receive. If arbitration was lost during the
address transfer stage, communication to the device
may be in progress. If addressed, an ACK pulse will be
generated. If arbitration was lost during the data trans-
fer stage, the device will need to retransfer the data at
a later time.
For more information on Multi-Master mode operation,
see AN578 - Use of the SSP Module in the I²C
Multi-Master Environment.
TABLE 9-3: REGISTERS ASSOCIATED WITH I²C OPERATION
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
0Bh, 8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF ^{0000 000x 0000 000u}
10Bh,18Bh
0Ch
PIR1
—
ADIF
—
— SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 0000 0000
8Ch
PIE1
—
ADIE
—
— SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 0000 0000
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
93h
SSPADD Synchronous Serial Port (I²C mode) Address Register
0000 0000 0000 0000
14h
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 ^{0000 0000 0000 0000}
94h
SSPSTAT SMP⁽¹⁾ CKE⁽¹⁾ D/A
P
S
R/W
UA
BF ^{0000 0000 0000 0000}
87h
TRISC ^{PORTC Data Direction Register}
1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’.
Shaded cells are not used by SSP module in SPI mode.
Note 1: Maintain these bits clear in I²C mode.
© 2007 Microchip Technology Inc.
DS39597C-page 51