PIC16F72-E Datasheet, PDF (30/136 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH Microcontoller with A/D Converter

PIC16F72
4.3 Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 TOSC (and
a small RC delay of 20 ns) and low for at least 2 TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
4.4 Prescaler
There is only one prescaler available, which is mutually
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
Timer0 module means that there is no prescaler for the
Watchdog Timer, and vice-versa. This prescaler is not
readable or writable (see Figure 4-1).
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
Note:
Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count but will not change the prescaler
assignment.
TABLE 4-1: REGISTERS ASSOCIATED WITH TIMER0
Address Name Bit 7 Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
01h,101h TMR0 Timer0 Module Register
xxxx xxxx uuuu uuuu
0Bh,8Bh, INTCON GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u
10Bh,18Bh
81h,181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
DS39597C-page 28
© 2007 Microchip Technology Inc.