PIC16F72-E Datasheet, PDF (41/136 Pages) Microchip Technology – 28-Pin, 8-Bit CMOS FLASH Microcontoller with A/D Converter

8.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven High
• Driven Low
• Remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
The output may become inverted when the mode of the
module is changed from Compare/Clear on Match
(CCPxM<3:0> = ‘1001’) to Compare/Set on Match
(CCPxM<3:0> = ‘1000’). This may occur as a result of
any operation that selectively clears bit CCPxM0, such
as a BCF instruction.
When this condition occurs, the output becomes
inverted when the instruction is executed. It will remain
inverted for all following Compare operations, until the
module is reset.
FIGURE 8-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Special event trigger will:
• RESET Timer1, but not set interrupt flag bit TMR1IF
(PIR1<0>)
• Set bit GO/DONE (ADCON0<2>) bit, which starts an A/D
conversion
Special Event Trigger
Set Flag bit CCP1IF
(PIR1<2>)
CCPR1H CCPR1L
Q
RC2/CCP1
pin
TRISC<2>
Output Enable
S _Output
Logic
R
Match
CCP1CON<3:0>
Mode Select
Comparator
TMR1H TMR1L
PIC16F72
8.2.1 CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an
output by clearing the TRISC<2> bit.
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
8.2.2 TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3 SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
8.2.4 SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
that may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special trigger output of CCP1 resets the TMR1
register pair, and starts an A/D conversion (if the A/D
module is enabled).
Note:
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
© 2007 Microchip Technology Inc.
DS39597C-page 39