PIC24FV32KA304 Datasheet, PDF (51/322 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

TABLE 4-21: CRC REGISTER MAP
File
Name
Addr
Bit 15
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
CRCCON1
0640 CRCEN
—
CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN —
CRCCON2
0642
—
—
— DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 —
—
—
PLEN4 PLEN3 PLEN2
CRCXORL
0644
X15
X14
X13
X12
X11
X10
X9
X8
X7
X6
X5
X4
X3
X2
CRCXORH
0646
X31
X30
X29
X28
X27
X26
X25
X24
X23
X22
X21
X20
X19
X18
CRCDATL
0648
CRCDATL
CRCDATH
064A
CRCDATH
CRCWDATL 064C
CRCWDATL
CRCWDATH 064E
CRCWDATH
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
PLEN1
X1
X17
—
PLEN0
—
X16
0000
0000
0000
0000
xxxx
xxxx
xxxx
xxxx
TABLE 4-22: CLOCK CONTROL REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 7
Bit 6
Bit 5
RCON
0740 TRAPR IOPUWR SBOREN LVREN
—
DPSLP CM PMSLP EXTR
OSCCON 0742
—
COSC2 COSC1 COSC0
—
NOSC2 NOSC1 NOSC0 CLKLOCK
CLKDIV
0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0
—
OSCTUN
0748
—
—
—
—
—
—
—
—
—
REFOCON 074E ROEN
—
ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0
—
HLVDCON 0756 HLVDEN —
HLSIDL
—
—
—
—
—
VDIR
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values are dependent on type of Reset.
OSCCON register Reset values are dependent on configuration fuses and by type of Reset.
SWR
—
—
—
—
BGVST
SWDTEN
LOCK
—
TUN5
—
IRVST
Bit 4
WDTO
—
—
TUN4
—
—
Bit 3
Bit 2
Bit 1
Bit 0
All
Resets
SLEEP IDLE
CF SOSCDRV
—
—
TUN3
TUN2
—
—
HLVDL3 HLVDL2
BOR
SOSCEN
—
TUN1
—
HLVDL1
POR (Note 1)
OSWEN (Note 2)
—
3140
TUN0 0000
—
0000
HLVDL0 0000
TABLE 4-23: DEEP SLEEP REGISTER MAP
File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
DSCON
DSWAKE
DSGPR0
DSGPR1
Legend:
Note 1:
0758 DSEN —
—
—
—
—
— RTCCWDIS
075A —
—
—
—
—
—
—
DSINT0
075C
075E
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
The Deep Sleep registers DSGPR0 and DSGPR1 are only reset on a VDD POR event.
—
DSFLT
DSGPR0
DSGPR1
Bit 6
—
—
Bit 5 Bit 4
Bit 3
Bit 2
—
—
ULPWDIS
— DSWDT DSRTCC DSMCLR
Bit 1
DSBOR
—
Bit 0
All
Resets⁽¹⁾
RELEASE 0000
DSPOR 0000
0000
0000