PIC24FV32KA304 Datasheet, PDF (265/322 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

PIC24FV32KA304 FAMILY
TABLE 29-1: THERMAL OPERATING CONDITIONS
Rating
Operating Junction Temperature Range
Operating Ambient Temperature Range
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD –  IOH)
I/O Pin Power Dissipation:
PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL)
Maximum Allowed Power Dissipation
Symbol Min
TJ
-40
TA
-40
Typ Max Unit
—
+125
°C
—
+85
°C
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/JA
W
TABLE 29-2: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol Typ Max Unit Notes
Package Thermal Resistance, 20-Pin SPDIP
JA
62.4
—
°C/W
1
Package Thermal Resistance, 28-Pin SPDIP
JA
60
—
°C/W
1
Package Thermal Resistance, 20-Pin SSOP
JA
108
—
°C/W
1
Package Thermal Resistance, 28-Pin SSOP
JA
71
—
°C/W
1
Package Thermal Resistance, 20-Pin SOIC
JA
75
—
°C/W
1
Package Thermal Resistance, 28-Pin SOIC
JA
80.2
—
°C/W
1
Package Thermal Resistance, 20-Pin QFN
JA
43
—
°C/W
1
Package Thermal Resistance, 28-Pin QFN
JA
32
—
°C/W
1
Package Thermal Resistance, 44-Pin QFN
JA
29
—
°C/W
1
Package Thermal Resistance, 48-Pin UQFN
JA
—
—
°C/W
1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
TABLE 29-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
Operating temperature -40°C  TA  +85°C for Industrial
Para
m No.
Symbol
Characteristic
Min Typ⁽¹⁾ Max Units
Conditions
DC10 VDD
Supply Voltage
1.8
— 3.6 V For F devices
2.0
— 5.5V V For FV devices
DC12 VDR
RAM Data Retention
Voltage⁽²⁾
1.5
——V
DC16 VPOR VDD Start Voltage
VSS
to Ensure Internal
Power-on Reset Signal
— 0.7 V
DC17 SVDD VDD Rise Rate
0.05 — — V/ms 0-3.3V in 0.1s
to Ensure Internal
0-2.5V in 60 ms
Power-on Reset Signal
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: This is the limit to which VDD can be lowered without losing RAM data.
 2011 Microchip Technology Inc.
DS39995A-page 265