PIC24FV32KA304 Datasheet, PDF (223/322 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

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22.2 A/D Sampling Requirements
The analog input model of the 12-bit A/D Converter is
shown in Figure 22-2. The total sampling time for the
A/D is a function of the holding capacitor charge time.
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the voltage level on the analog input
pin. The source impedance (RS), the interconnect
impedance (RIC) and the internal sampling switch
(RSS) impedance combine to directly affect the time
required to charge CHOLD. The combined impedance of
the analog sources must, therefore, be small enough to
fully charge the holding capacitor within the chosen
sample time. To minimize the effects of pin leakage
currents on the accuracy of the A/D Converter, the
maximum recommended source impedance, RS, is
2.5 k. After the analog input channel is selected
(changed), this sampling function must be completed
prior to starting the conversion. The internal holding
capacitor will be in a discharged state prior to each
sample operation.
At least 1 TAD time period should be allowed between
conversions for the sample time. For more details, see
Section 29.0 “Electrical Characteristics”.
EQUATION 22-1: A/D CONVERSION CLOCK
PERIOD
TAD = TCYADCS + 1
ADCS = ^T----^A---^D-- – 1
TCY
Note: Based on TCY = 2/FOSC; Doze mode
and PLL are disabled.
FIGURE 22-2:
12-BIT A/D CONVERTER ANALOG INPUT MODEL
Rs ^ANx
VA
CPIN
RIC  250
Sampling
Switch
RSS
RSS  3 k
ILEAKAGE
500 nA
CHOLD
= 4.4 pF
VSS
Legend: CPIN
= Input Capacitance
VT
= Threshold Voltage
ILEAKAGE = Leakage Current at the pin due to
various junctions
RIC
= Interconnect Resistance
RSS
= Sampling Switch Resistance
CHOLD = Sample-and-Hold Capacitance (from DAC)
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs  5 k.
 2011 Microchip Technology Inc.
DS39995A-page 223