PIC24FV32KA304 Datasheet, PDF (131/322 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

PIC24FV32KA304 FAMILY
REGISTER 10-1: DSCON: DEEP SLEEP CONTROL REGISTER⁽¹⁾
R/W-0
U-0
U-0
U-0
U-0
U-0
DSEN
—
—
—
—
—
bit 15
U-0
R/W-0
—
RTCCWDIS
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/C-0, HS
—
—
—
—
—
ULPWUDIS DSBOR⁽²⁾
RELEASE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-9
bit 8
bit 7-3
bit 2
bit 1
bit 0
DSEN: Deep Sleep Enable bit
1 = Enters Deep Sleep on execution of PWRSAV #0
0 = Enters normal Sleep on execution of PWRSAV #0
Unimplemented: Read as ‘0’
RTCCWDIS: RTCC Wake-up Disable bit
1 = Wake-up from Deep Sleep with RTCC disabled
0 = Wake-up from Deep Sleep with RTCC enabled
Unimplemented: Read as ‘0’
ULPWUDIS: ULPWU Wake-up Disable bit
1 = Wake-up from Deep Sleep with ULPWU disabled
0 = Wake-up from Deep Sleep with ULPWU enabled
DSBOR: Deep Sleep BOR Event bit⁽²⁾
1 = The DSBOR was active and a BOR event was detected during Deep Sleep
0 = The DSBOR was not active, or was active but did not detect a BOR event during Deep Sleep
RELEASE: I/O Pin State Release bit
1 = Upon waking from Deep Sleep, I/O pins maintain their previous states to Deep Sleep entry
0 = Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRIS and
LAT bits to control their states
Note 1: All register bits are reset only in the case of a POR event outside of Deep Sleep mode.
2: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this re-arms
POR.
 2011 Microchip Technology Inc.
DS39995A-page 131