PIC24FV32KA304 Datasheet, PDF (160/322 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

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15.4 Subcycle Resolution
The DCB bits (OCxCON2<10:9>) provide for resolution
better than one instruction cycle. When used, they
delay the falling edge generated from a match event by
a portion of an instruction cycle.
For example, setting DCB<1:0> = 10 causes the falling
edge to occur halfway through the instruction cycle in
which the match event occurs, instead of at the
beginning. These bits cannot be used when
OCM<2:0> = 001. When operating the module in PWM
mode (OCM<2:0> = 110 or 111), the DCB bits will be
double-buffered.
The DCB bits are intended for use with a clock source
identical to the system clock. When an OCx module
with enabled prescaler is used, the falling edge delay
caused by the DCB bits will be referenced to the
system clock period rather than the OCx module’s
period.
TABLE 15-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)⁽¹⁾
PWM Frequency
7.6 Hz
61 Hz
122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz
Prescaler Ratio
8
1
1
1
Period Value
FFFFh
FFFFh
7FFFh
0FFFh
Resolution (bits)
16
16
15
12
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
1
03FFh
10
1
007Fh
7
1
001Fh
5
TABLE 15-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)⁽¹⁾
PWM Frequency
30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz
Prescaler Ratio
8
1
1
1
Period Value
FFFFh
FFFFh
7FFFh
0FFFh
Resolution (bits)
16
16
15
12
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
1
03FFh
10
1
007Fh
7
1
001Fh
5
DS39995A-page 160
 2011 Microchip Technology Inc.