PIC24FV32KA304 Datasheet, PDF (178/322 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

PIC24FV32KA304 FAMILY
REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0, HSC R-0, HSC U-0
U-0
ACKSTAT TRSTAT
—
—
bit 15
U-0
R/C-0, HS
—
BCL
R-0, HSC
GCSTAT
R-0, HSC
ADD10
bit 8
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC
IWCOL I2COV
D/A
P
bit 7
R/C-0, HSC
S
R-0, HSC
R/W
R-0, HSC
RBF
R-0, HSC
TBF
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13-11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
ACKSTAT: Acknowledge Status bit
1 = NACK was detected last
0 = ACK was detected last
Hardware is set or clear at end of Acknowledge.
TRSTAT: Transmit Status bit
(When operating as I²C master; applicable to master transmit operation.)
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
Hardware is set at beginning of master transmission; hardware is clear at end of slave Acknowledge.
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1 = A bus collision has been detected during a master operation
0 = No collision
Hardware is set at detection of bus collision.
GCSTAT: General Call Status bit
1 = General call address was received
0 = General call address was not received
Hardware is set when address matches general call address; hardware is clear at Stop detection.
ADD10: 10-Bit Address Status bit
1 = 10-bit address was matched
0 = 10-bit address was not matched
Hardware is set at match of 2^nd byte of matched 10-bit address; hardware is clear at Stop detection.
IWCOL: Write Collision Detect bit
1 = An attempt to write to the I2C1TRN register failed because the I²C module is busy
0 = No collision
Hardware is set at occurrence of write to I2C1TRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1 = A byte was received while the I2C1RCV register is still holding the previous byte
0 = No overflow
Hardware is set at attempt to transfer I2C1RSR to I2C1RCV (cleared by software).
D/A: Data/Address bit (when operating as I²C slave)
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was the device address
Hardware is clear at device address match; hardware is set by write to I2C1TRN or by reception of slave byte.
P: Stop bit
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
Hardware is set or cleared when Start, Repeated Start or Stop detected.
DS39995A-page 178
 2011 Microchip Technology Inc.