PIC24FV32KA304 Datasheet, PDF (248/322 Pages) Microchip Technology – 20/28/44/48-Pin, General Purpose, 16-Bit Flash Microcontrollers with XLP Technology

PIC24FV32KA304 FAMILY
26.2 On-Chip Voltage Regulator
All of the PIC24FV32KA304 family of devices power
their core digital logic at a nominal 3.0V. This may
create an issue for designs that are required to operate
at a higher typical voltage, as high as 5.0V. To simplify
system design, all devices in the ‘‘FV’’ family incorpo-
rate an on-chip regulator that allows the device to run
its core logic from VDD.
The regulator is always enabled and provides power to
the core from the other VDD pins. A low-ESR capacitor
(such as ceramic) must be connected to the VCAP pin
(Figure 26-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Section 29.1 “DC Characteristics”.
In all of the PIC24FJ64GA family of devices, the
regulator is disabled.
For the ‘‘F’’ devices, the VDDCORE and VDD pins are
internally tied together to operate at an overall lower
allowable voltage range (1.8-3.6V). Refer to Figure 26-1
for possible configurations.
26.2.1
VOLTAGE REGULATOR TRACKING
MODE AND LOW-VOLTAGE
DETECTION
For all PIC24FV32KA304 devices, the on-chip regula-
tor provides a constant voltage of 3.0V nominal to the
digital core logic. The regulator can provide this level
from a VDD of about 3.0V, all the way up to the device’s
VDDMAX. It does not have the capability to boost VDD
levels below 3.0V. In order to prevent “brown out” con-
ditions when the voltage drops too low for the regulator,
the regulator enters Tracking mode. In Tracking mode,
the regulator output follows VDD with a typical voltage
drop of 100 mV.
When the device enters Tracking mode, it is no longer
possible to operate at full speed. To provide information
about when the device enters Tracking mode, the
on-chip regulator includes a simple, High/Low-Voltage
Detect (HLVD) circuit. When VDD drops below full-speed
operating voltage, the circuit sets the High/Low-Voltage
Detect Interrupt Flag, HLVDIF (IFS4<8>). This can be
used to generate an interrupt and put the application into
a low-power operational mode or trigger an orderly
shutdown. High/Low-Voltage Detection is only available
for ‘‘FV’’ parts.
FIGURE 26-1:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
Regulator Enabled:
5.0V
PIC24FV32KA304
VDD
CEFC
(10 F typ)
VCAP
VSS
Note 1:
These are typical operating voltages. Refer to
Section 29.0 “Electrical Characteristics” for
the full operating ranges of VDD and VDDCORE.
26.2.2 ON-CHIP REGULATOR AND POR
For PIC24FV32KA304 devices, it takes approximately
1 s for it to generate output. During this time, desig-
nated as TPM, code execution is disabled. TPM is
applied every time the device resumes operation after
any power-down, including Sleep mode.
26.3 Watchdog Timer (WDT)
For the PIC24FV32KA304 family of devices, the WDT
is driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT time-out period (TWDT) of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the Configuration bits,
WDTPS<3:0> (FWDT<3:0>), which allow the selection
of a total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler time-out periods, ranging
from 1 ms to 131 seconds, can be achieved.
DS39995A-page 248
 2011 Microchip Technology Inc.