PIC24F08KA102-I Datasheet, PDF (234/278 Pages) Microchip Technology – 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology

PIC24F16KA102 FAMILY
TABLE 29-22: AC SPECIFICATIONS
Symbol
Characteristics
Min
Typ
Max
Units
TLW
BCLKx High Time
20
TCY/2
—
ns
THW
BCLKx Low Time
20
(TCY * BRGx) + TCY/2
—
ns
TBLD
BCLKx Falling Edge Delay from UxTX
-50
—
50
ns
TBHD
BCLKx Rising Edge Delay from UxTX
TCY/2 – 50
—
TCY/2 + 50 ns
TWAK
Min. Low on UxRX Line to Cause Wake-up
—
1
—
s
TCTS
Min. Low on UxCTS Line to Start
Transmission
TCY
—
—
ns
TSETUP Start bit Falling Edge to System Clock Rising
3
—
Edge Setup Time
—
ns
TSTDELAY Maximum Delay in the Detection of the
—
Start bit Falling Edge
—
TCY + TSETUP ns
TABLE 29-23: A/D CONVERSION TIMING REQUIREMENTS⁽¹⁾
A/D CHARACTERISTICS
Standard Operating Conditions: 1.8V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +125°C for Extended
Param
No.
Symbol
Characteristic
Min. Typ Max. Units
Conditions
AD50 TAD
AD51 TRC
A/D Clock Period
Clock Parameters
75 —
—
A/D Internal RC Oscillator Period
— 250 —
ns TCY = 75 ns, AD1CON3
is in the default state
ns
AD55
AD56
AD57
AD58
AD59
TCONV
FCNV
TSAMP
TACQ
TSWC
AD60 TDIS
Conversion Rate
Conversion Time
— 12
Throughput Rate
——
Sample Time
—
1
Acquisition Time
750 —
Switching Time from Convert to
Sample
——
Discharge Time
0.5 —
—
500
—
—
(Note 3)
—
TAD
ksps
TAD
ns
TAD
AVDD  2.7V
(Note 2)
Clock Parameters
AD61 TPSS
Sample Start Delay from Setting
Sample bit (SAMP)
2
—
3
TAD
Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
2: The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD).
3: On the following cycle of the device clock.
DS39927C-page 234
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