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PIC24F08KA102-I Datasheet, PDF (105/278 Pages) Microchip Technology – 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology | |||
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PIC24F16KA102 FAMILY
REGISTER 10-1: DSCON: DEEP SLEEP CONTROL REGISTER(1)
R/W-0
U-0
U-0
U-0
U-0
U-0
U-0
DSEN
â
â
â
â
â
â
bit 15
U-0
â
bit 8
U-0
U-0
U-0
â
â
â
bit 7
U-0
U-0
U-0
R/W-0
R/C-0, HS
â
â
â
DSBOR(2)
RELEASE
bit 0
Legend:
R = Readable bit
-n = Value at POR
C = Clearable bit
W = Writable bit
â1â = Bit is set
HS = Hardware Settable bit
U = Unimplemented bit, read as â0â
â0â = Bit is cleared x = Bit is unknown
bit 15
bit 14-2
bit 1
bit 0
DSEN: Deep Sleep Enable bit
1 = Enters Deep Sleep on execution of PWRSAV #0
0 = Enters normal Sleep on execution of PWRSAV #0
Unimplemented: Read as â0â
DSBOR: Deep Sleep BOR Event bit(2)
1 = The DSBOR was active and a BOR event was detected during Deep Sleep
0 = The DSBOR was not active, or was active but did not detect a BOR event during Deep Sleep
RELEASE: I/O Pin State Release bit
1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry
0 = Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRIS and
LAT bits to control their states
Note 1: All register bits are reset only in the case of a POR event outside of Deep Sleep mode.
2: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this
re-arms POR.
ï£ 2008-2011 Microchip Technology Inc.
DS39927C-page 105
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