PIC16F676-I Datasheet, PDF (22/132 Pages) Microchip Technology – 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers

PIC16F630/676
REGISTER 3-2:
TRISA — PORTA TRI-STATE REGISTER (ADDRESS: 85h)
U-0
—
bit 7
U-0
R/W-x R/W-x
R-1
R/W-x R/W-x R/W-x
—
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
bit 0
bit 7-6:
bit 5-0:
Unimplemented: Read as ‘0’
TRISA<5:0>: PORTA Tri-State Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Note: TRISA<3> always reads 1.
REGISTER 3-3:
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
WPUA — WEAK PULL-UP REGISTER (ADDRESS: 95h)
U-0
—
bit 7
U-0
R/W-1 R/W-1
U-0
R/W-1
—
WPUA5 WPUA4
—
WPUA2
R/W-1
WPUA1
R/W-1
WPUA0
bit 0
bit 7-6
bit 5-4
bit 3
bit 2-0
Unimplemented: Read as ‘0’
WPUA<5:4>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
WPUA<2:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRISA = 0).
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
3.2.2 INTERRUPT-ON-CHANGE
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits IOCAx enable
or disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set, the PORTA Change Interrupt flag
bit (RAIF) in the INTCON register.
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTA. This will end the
mismatch condition.
b) Clear the flag bit RAIF.
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
DS40039F-page 22
 2010 Microchip Technology Inc.