PIC24HJ128GP206-I Datasheet, PDF (155/286 Pages) Microchip Technology – High-Performance, 16-Bit Microcontrollers

PIC24HJXXXGPX06/X08/X10
16.0 INTER-INTEGRATED CIRCUIT
(I²C)
Note:
This data sheet summarizes the features
of this group of PIC24HJXXXGPX06/X08/
X10 devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to the “PIC24H Family Reference
Manual”. Refer to the Microchip web site
(www.microchip.com) for the latest
PIC24H Family Reference Manual
sections.
The Inter-Integrated Circuit (I²C) module provides
complete hardware support for both Slave and Multi-
Master modes of the I²C serial communication
standard, with a 16-bit interface.
The PIC24HJXXXGPX06/X08/X10 devices have up to
two I²C interface modules, denoted as I2C1 and I2C2.
Each I²C module has a 2-pin interface: the SCLx pin is
clock and the SDAx pin is data.
Each I²C module ‘x’ (x = 1 or 2) offers the following key
features:
• I²C interface supporting both master and slave
operation.
• I²C Slave mode supports 7 and 10-bit address.
• I²C Master mode supports 7 and 10-bit address.
• I²C port allows bidirectional transfers between
master and slaves.
• Serial clock synchronization for I²C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
• I²C supports multi-master operation; detects bus
collision and will arbitrate accordingly.
16.1 Operating Modes
The hardware fully implements all the master and slave
functions of the I²C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
The I²C module can operate either as a slave or a
master on an I²C bus.
The following types of I²C operation are supported:
• I²C slave operation with 7-bit address
• I²C slave operation with 10-bit address
• I²C master operation with 7 or 10-bit address
For details about the communication sequence in each
of these modes, please refer to the “PIC24H Family
Reference Manual”.
16.2 I²C Registers
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write.
I2CxRSR is the shift register used for shifting data,
whereas I2CxRCV is the buffer register to which data
bytes are written, or from which data bytes are read.
I2CxRCV is the receive buffer. I2CxTRN is the transmit
register to which bytes are written during a transmit
operation.
The I2CxADD register holds the slave address. A
status bit, ADD10, indicates 10-bit Address mode. The
I2CxBRG acts as the Baud Rate Generator (BRG)
reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV
and an interrupt pulse is generated.
16.3 I²C Interrupts
The I²C module generates two interrupt flags, MI2CxIF
(I²C Master Events Interrupt Flag) and SI2CxIF (I²C
Slave Events Interrupt Flag). A separate interrupt is
generated for all I²C error conditions.
16.4 Baud Rate Generator
In I²C Master mode, the reload value for the BRG is
located in the I2CxBRG register. When the BRG is
loaded with this value, the BRG counts down to ‘0’ and
stops until another reload has taken place. If clock arbi-
tration is taking place, for instance, the BRG is reloaded
when the SCLx pin is sampled high.
As per the I²C standard, FSCL may be 100 kHz or
400 kHz. However, the user can specify any baud rate
up to 1 MHz. I2CxBRG values of ‘0’ or ‘1’ are illegal.
EQUATION 16-1: SERIAL CLOCK RATE
( ) I2CxBRG =
FCY
FSCL
–10,F0^C₀^Y_0,000
–1
© 2007 Microchip Technology Inc.
DS70175F-page 153