PIC24HJ128GP206-I Datasheet, PDF (141/286 Pages) Microchip Technology – High-Performance, 16-Bit Microcontrollers

PIC24HJXXXGPX06/X08/X10
13.0 INPUT CAPTURE
Note:
This data sheet summarizes the features
of this group of PIC24HJXXXGPX06/X08/
X10 devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to the “PIC24H Family Reference
Manual”. Refer to the Microchip web site
(www.microchip.com) for the latest
PIC24H Family Reference Manual
sections.
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The PIC24HJXXXGPX06/X08/X10 devices support up
to eight input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
1. Simple Capture Event modes
-Capture timer value on every falling edge of
input at ICx pin
-Capture timer value on every rising edge of
input at ICx pin
2. Capture timer value on every edge (rising and
falling)
3. Prescaler Capture Event modes
-Capture timer value on every 4th rising edge
of input at ICx pin
-Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
• Input capture can also be used to provide
additional sources of external interrupts
Note:
Only IC1 and IC2 can trigger a DMA data
transfer. If DMA data transfers are
required, the FIFO buffer size must be set
to 1 (ICI<1:0> = 00).
FIGURE 13-1:
INPUT CAPTURE BLOCK DIAGRAM
From 16-bit Timers
TMRy TMRz
ICx Pin
Prescaler
Counter
(1, 4, 16)
Edge Detection Logic
and
Clock Synchronizer
3
ICM<2:0> (ICxCON<2:0>)
Mode Select
ICOV, ICBNE (ICxCON<4:3>)
ICxI<1:0>
ICxCON
FIFO
R/W
Logic
Interrupt
Logic
16 16
1
0
ICTMR
(ICxCON<7>)
ICxBUF
System Bus
Set Flag ICxIF
(in IFSn Register)
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
© 2007 Microchip Technology Inc.
DS70175F-page 139