MAX11043 Datasheet, PDF (7/33 Pages) Maxim Integrated Products – 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC

4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
ELECTRICAL CHARACTERISTICS (continued)
(V_AVDD = +3.0V to +3.6V, V_DVDD = +3.0V, C_DVREG = 10µF, V_AGND = V_DGND = 0V, common-mode input voltage = V_AVDD/2, V_REFBP
= V_REFA = V_REFB = V_REFC = V_REFD = +2.5V (external reference), V_REFDAC = V_REFDACH = +1.25V (external reference), V_REFDACL =
0V, C_REFBP = C_REFA = C_REFB = C_REFC = C_REFD = C_REFDAC = 1µF, f_SCLK = 38.4MHz, f_EXCLK = 38.4MHz (external clock applied to
OSCIN), clock divider set to 4, SHDN = DACSTEP = UP/DWN = DGND, CONVRUN = DVDD, all analog inputs driven directly through
a series 150Ω/330pF anti-alias filter, PGA gain = 1. Default filters and gain settings. DIFF = 1. T_A = T_MIN to T_MAX, unless otherwise noted
(Note 1). Typical values are at T_A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
SPI INTERFACE
SCLK Clock Period
t_CP
SCLK Pulse-Width High
t_CH
25
ns
10
ns
SCLK Pulse-Width Low
SCLK Rise to DOUT Transition
CS Fall to SCLK Rise Setup Time
SCLK Rise to CS Rise Setup Time
t_CL
t_DOT
t_CSS
t_CSH
C_LOAD = 20pF
10
ns
1
15
ns
10
ns
5
ns
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
CS Pulse-Width High
CS Rise to DOUT Disable
CS Fall to DOUT Enable
EOC Fall to CS Fall
t_DS
t_DH
t_CSPWH
t_DOD
t_DOE
t_RDS
C_LOAD = 20pF
C_LOAD = 20pF
10
ns
0
ns
10
ns
20
ns
1
ns
10
ns
Note 1: Devices 100% production tested at T_A = +125°C. Guaranteed by design and characterization to T_A = -40°C.
Note 2: Full scale in analog EQ mode decreases with increasing frequency at a rate of 20dB/decade from 8kHz. If digital EQ is also
used, full scale decreases with increasing frequency at 40dB/decade from 5kHz.
Note 3: SFDR in the EQ mode is normalized to the input by subtracting the analog EQ gain at each frequency (20dB/decade) from
the FFT results.
Note 4: The absolute input voltage range is 0 to AVDD. For optimal performance, use a common-mode voltage of AVDD/2.
Note 5: Switched capacitor input impedance is proportional to 1/fC. Where f is the sampling frequency and C is the input capacitance.
Typical Operating Characteristics
(V_AVDD = +3.3V, V_DVDD = +3.0V, f_SCLK = f_EXCLK = 19.2MHz, V_REFBP, V_{REF_} = +2.5V, common-mode input voltage = V_AVDD/2,
T_A = +25°C, unless otherwise noted.)
400ksps FFT
800ksps FFT
INL vs. CODE
LP MODE
LP MODE
5
0
0
4
3
LP MODE
GAIN = 1
-20
f_IN = 50kHz
GAIN = 1
-20
f_IN = 50kHz
GAIN = 1
2
-40
-40
1
-60
0
-60
-1
-80
-2
-80
-100
-3
-100
-4
-120
-5
-120
0
16384 32768 49152 65536
0 20 40 60 80 100 120 140 160 180 200
CODE (LSB)
FREQUENCY (kHz)
-140
0
50 100 150 200 250 300 350 400
FREQUENCY (kHz)
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