MAX11043 Datasheet, PDF (19/33 Pages) Maxim Integrated Products – 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC

4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Register Functions
ADCA, ADCB, ADCC, and ADCD
Result Registers (00h–03h)
The ADC channel A, B, C, and D result registers pro-
vide the result data from the 4 ADC channels. EOC
asserts low when new data is available. Initiate a data
read prior to the next rising edge of EOC or the result is
overwritten. Set bit 5 of the configuration register 08h
high to read the data out in 24-bit resolution or set bit 5
low to read the data out in 16-bit resolution.
ADCAB, ADCCD, and ADCABCD
Result Registers (04h–06h)
Registers ADCAB, ADCCD, and ADCABCD contain
concatenated ADC results ensuring simultaneous
results are read. This reduces the risk of reading sam-
ples delayed by one cycle from channel to channel.
Set bit 5 of the configuration register 08h high to read
the data out in 24-bit resolution or set bit 5 low to read
the data out in 16-bit resolution.
Status Register (07h)
BIT 7
X
BIT 6
X
BIT 5
Flash Busy
BIT 4
BOOT
The status register contains the channel overflow flags
and POR bits.
X<7:6>: Don’t-care bits.
Flash Busy<5>: Do not start a new flash operation until
this is 0.
BIT 3
OFLGA
BIT 2
OFLGB
BIT 1
OFLGC
BIT 0
OFLGD
BOOT<4>: Power-on reset flag.
OFLG_<3:0>: Channel overflow flag, one per channel.
Configuration Register (08h)
BIT 15
EXTCLK
BIT 14
CLKDIV1
BIT 13
CLKDIV0
BIT 12
PD
BIT 11
PDA
BIT 10
PDB
BIT 9
PDC
BIT 8
PDD
BIT 7
PDDAC
BIT 6
PDOSC
BIT 5
24BIT
BIT 4
SCHANA
EXTCLK<15>: External clock select.
1 = logic-level clock supplied on OSCIN.
0 = crystal or resonator connected between OSCIN
and OSCOUT (default).
CLKDIV1:CLKDIV0<14:13>: Clock divider ratio (EX
clock : ADC sample clock).
00 = 1:2 clock divider.
01 = 1:3 clock divider.
10 = 1:4 clock divider.
11 = 1:6 clock divider (default).
PD<12>: Power-down analog circuitry (reference and
SPI interface remains active).
1 = low-power mode.
0 = normal operation (default).
BIT 3
SCHANB
BIT 2
SCHANC
BIT 1
SCHAND
BIT 0
DECSEL
PD_<11:8>: ADC power-down for each channel (A, B,
C, and D).
1 = powers down analog signal path.
0 = normal operation (default).
PDDAC< 7>: DAC power-down.
1 = fine DAC buffer powered down.
0 = normal operation (default).
PDOSC<6>: Oscillator power-down.
1 = oscillator powered down (disconnects EX clock in
EX clock mode).
0 = normal operation (default).
24BIT<5>: ADC output data format.
1 = ADC data output as 24 bits.
0 = ADC data output as 16 bits (default).
Use the 24-bit ADC output in conjunction with external
digital filtering to improve signal-to-noise ratio.
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