MAX11043 Datasheet, PDF (16/33 Pages) Maxim Integrated Products – 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC

4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Reference (REFBP)
The MAX11043 features an internal 2.5V bandgap ref-
erence. Bypass REFBP with a 1µF capacitor or power
down the buffer amplifier and drive REFBP with an
external reference. In internal reference mode, REFBP
provides the main reference voltage for the MAX11043.
Refer to www.maxim-ic.com/references for a list of
available precision references.
In addition to the integrated main reference, there are
seven separate references derived from REFBP, one for
each ADC channel, one for the coarse DAC, and two
(one high and one low) for the fine DAC. When using
the main reference, bypass each of the references with
a 1µF capacitor or set the appropriate bits (7–0), in the
reference (10h) register, to power down the references
and drive externally. Use external references capable
of driving a 700µA or total load.
Clock Sources
The MAX11043 features an internal 16MHz oscillator
that supports either an external crystal or ceramic res-
onator. For highest performance, set bit 15 in the con-
figuration register to 1 and use an external clock (EX
clock) source, up to 40MHz, to drive OSCIN. A pro-
grammable clock divider divides the EX clock by 2, 3,
4, or 6 to generate the ADC sample clock. The system
clock, used for all digital timing, is twice the ADC sam-
ple clock. Ensure that the minimum EX clock high or
low time is greater than 25ns when using the divide-by-
2 or divide-by-3 mode.
The system clock, used for all internal timing, is derived
from the clock divider setting and the input clock.
For optimal performance, derive the SPI clock and sys-
tem clock from the same source.
Power Saving
The MAX11043 features an active-high power-down
input, as well as an SPI-controlled power-down bit that
places the MAX11043 in low-power mode. In addition,
the MAX11043 features an independent, SPI-controlled,
power-down for each ADC channel, the DAC, and the
oscillator. See the Configuration Register (08h) section
for more details.
Serial Communication
The SPI-compatible interface allows synchronous serial
data transfers up to 40Mbps. The bandwidth is divided
between the DACs and the ADC. Maximum conversion
throughput depends on which read commands are
used. The highest conversion rates are obtained by
using the scan mode. The second highest rate is
obtained by reading concatenated registers. The slow-
est method is to read the results individually.
Configure the SPI master for SCLK to idle low (SCLK is
low when CS is asserted). The data at DIN is latched on
the rising edge of SCLK. Data at DOUT transitions
immediately after the rising edge of SCLK.
All SPI transactions start with a command byte. The
command byte selects the address of the register and
the mode of operation (read/write).
SPI Command Byte
BIT 7
START
BIT 6
ADR4
BIT 5
ADR3
BIT 4
ADR2
START<7>: Start bit. This bit must be 0 for normal
operation.
ADR_<6:2>: Device register address bits. See the reg-
ister map in Table 2.
BIT 3
ADR1
BIT 2
ADR0
BIT 1
R/W
BIT 0
0
R/W<1>: Read/write bit. 1 = read from device. 0 = write
to device.
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