MAX11043 Datasheet, PDF(25/33 Page) Maxim Integrated Products – 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC

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MAX11043 Datasheet, PDF (25/33 Pages) Maxim Integrated Products – 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC

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4-Channel, 16-Bit, Simultaneous-Sampling ADCs

with PGA, Filter, and 8-/12-Bit Dual-Stage DAC

Flash Data In Register (1Ah)

Write allowed only if flash busy bit is zero.

This is a 16-bit register that contains the data for a flash

write operation. Default = 0.

Flash Data Out Register (1Bh)

This is a read-only register. Data is valid only if flash

busy is zero.

This is a 16-bit register that contains the data for a flash

read operation.

Flash and C-RAM Register Map

The flash memory consists of 2048 words by 16 bits. The

3 MSBs of the flash address select one of eight pages of

256 words each. Page zero contains the default filter

coefficients for channels A and B. Page one contains the

default filter coefficients for channels C and D. Use

pages two and three for the coefficients of custom filters.

When the first word on page two contains a nonzero

value, the MAX11043 loads these pages into C-RAM at

power-up instead of the default values from pages zero

and one. Flash pages zero and one include trim data.

Unique trim data optimizes the performance of each

MAX11043. Coefficients for the stage 1 filters and ADC

gain are individually programmed at the factory to com-

pensate for manufacturing variations in the analog por-

tion of the IC. These coefficients vary depending on the

PGA gain setting and if the analog equalizer is used. To

allow for these different modes, several sets of stage 1

coefficients are stored in flash. Bits in the CONGIF reg-

ister select which set of stage 1 coefficients are used.

Table 3 shows the C-RAM addresses used for each

CONFIG setting. To maintain optimum performance

when using custom filters, copy the trim data from flash

pages zero and one to the corresponding locations in

flash pages two and three or to C-RAM when writing

directly to C-RAM.

For custom filters, use stages 2â7 first, and only change

the stage 1 coefficients when all seven stages require

customization.

To load the coefficients directly to C-RAM, create a 32-

bit data word by concatenating the data in adjacent

flash locations as shown in Table 3. The C-RAM

addresses below are for channel A; for channel B add

40h, for channel C add 80h, and for channel D add C0h.

Multiple addresses exist for some stage 1 filter coeffi-

cients as shown in Table 4. The address accessed by

the filter depends on the configuration bits as shown in

Table 3.

Table 3. Stage 1 Filter Selection

STAGE 1 COEFFICIENT ADDRESS

PDPGA

MODG

PGAG

EQ filter stage 1 (C-RAM address 03hâ05h)

LP filter for ADC gain of 1, 2, and 4; stage 1 (C-RAM address 1Dhâ1Fh)

LP filter for ADC gain of 8; stage 1 (C-RAM address 3Dhâ3Fh)

LP filter for ADC gain of 16; stage 1 (C-RAM address 23hâ25h)

Table 4. C-RAM and Flash Memory Map for Channel A Flash Page One*

C-RAM

FLASH

ADDRESS ADDRESS

MSB FOR C-RAM

LSB FOR C-RAM

00h

01h*

EQ gain trim for gain = 1

Not used

02h

Not used

01h

03h

User trim for EQ gain, default = 2000h

04h

02h

05h

Not used

06h*

EQ filter gain for filter stage 1

03h

07h*

EQ filter coefficient -A2 for filter stage 1

*For channel B add 80h, for channel C add 100h, and for channel D add 180h. To write to pages two and three of flash, add 200h to

these values.

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