MAX11043 Datasheet, PDF (23/33 Pages) Maxim Integrated Products – 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC

4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
Fine Gain A/B/C/D Registers (11h–14h)
Fine gain for each channel is a two’s complement binary value (8192 x desired gain).
FINE GAIN REGISTER
7FFFh
4000h
2001h
2000h
1FFFh
1000h
0800h
GAIN
(4 – 1/8192)
2
8193/8192
1 (default)
8191/8192
0.5
0.25
Filter Coefficient Address Register (15h)
BIT 7
CHAN1
BIT 6
CHAN0
BIT 5
ADR5
BIT 4
ADR4
CHAN_<7:6>: Channel selection.
00 = channel A (default).
01 = channel B.
10 = channel C.
11 = channel D.
ADR5:ADR0<5:0>: Address pointer for C-RAM con-
taining filter coefficients (default = 0).
BIT 3
ADR3
BIT 2
ADR2
BIT 1
ADR1
BIT 0
ADR0
Filter Coefficient Data Out Register (16h)
This is a 32-bit register that contains the data from a
C-RAM read operation.
Filter Coefficient Data In Register (17h)
This is a 32-bit register that contains the data for a C-RAM
write operation. Default = 0.
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