MAX11043 Datasheet, PDF (13/33 Pages) Maxim Integrated Products – 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC

4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
modulator running at 9.6Msps. Operating the modulator
at a lower sample rate causes a proportional reduction
in the frequency response of the sinc 5 filter. The total
attenuation of the MAX11043 is the sum of the analog
filtering, the sinc 5 filter, and the seven stages of pro-
grammable filters.
Equalizer (EQ)
The EQ matches the frequency/gain characteristics of
CW-chirp radar systems where the distance to the tar-
get is proportional to the measured frequency. Distant
targets not only have a higher frequency, they have a
weaker signal. Hence, higher frequencies need more
amplification than lower frequencies. The EQ provides
gain proportional to frequencies up to 190kHz, at which
point the gain rolls off at 80dB/decade.
The EQ consists of an analog section in the PGA and a
digital EQ created from the biquad filters. The analog
EQ (PGA) provides 20dB/decade of gain and the
default digital EQ provides an additional 20dB/decade
of gain. Together they provide 40dB/decade of gain up
to 190kHz with a gain of 0dB at 5kHz.
Variations in the manufacturing process affect the gain
and phase of the analog filter. Compensation for these
variations include adjustments to the digital filter during
the manufacture of the MAX11043. Use the analog and
digital EQs together for optimal performance.
Conversion and ADC Reading
Drive CONVRUN high to initiate a continuous conver-
sion on all 4 channels. Keep CONVRUN high for the
entire conversion process. Do not pulse CONVRUN.
EOC asserts low when new data is available. Initiate a
data read prior to the next rising edge of EOC or the
result is overwritten. EOC asserts high upon read com-
pletion of all active channels. Use ConfigA, ConfigB,
ConfigC, and ConfigD registers to read single channel
data. Concatenated data is available in the ADCAB,
ADCCD, and ADCABCD registers. Use concatenated
registers to ensure simultaneous results are read. See
the Register Functions section for more details.
A software-selectable scan mode automatically sends
the result from selected channels following the CS
falling edge and allows other registers to be simultane-
ously updated. To enable scan mode, set SCHAN_ bits
high. See the Configuration Register (08h) section for a
detailed description. The ADC output is presented in
two’s complement format (Figure 3).
Digital Filter
Seven cascaded, individually configurable, 2nd-order
filter elements make up the digital filter. Figure 4 shows
the structure of a single filter section. Configure these
elements as LP, BP, HP, or all pass (AP) filters with
optional rectification. Filter configuration is transferred
from the flash to coefficient RAM (C-RAM) on power-up.
Store custom filters permanently in the flash or write
directly to C-RAM each time on power-up. Two sepa-
rate sets of programmable coefficients exist for each
filter. Dual coefficient sets allow rapid filter reconfigura-
tion. These filter coefficients are programmed to LP and
EQ modes at the factory. Multiple flash memory pages
exist so that custom filters can be created while pre-
serving factory-programmed filter coefficients.
SINC 5 FILTER AT 9.6Msps
0
-20
-40
-60
-80
0111 1111 1111 1111
0111 1111 1111 1110
0111 1111 1111 1101
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
-100
-120
0
400 800 1200 1600 2000
FREQUENCY (kHz)
1000 0000 0000 0010
1000 0000 0000 0001
1000 0000 0000 0000
-FS
-1 0 +1
+FS
INPUT VOLTAGE (LSB)
Figure 2. Sinc 5 Filter Frequency Response
Figure 3. Two’s Complement Transfer Function
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