MAX11043 Datasheet, PDF (21/33 Pages) Maxim Integrated Products – 4-Channel, 16-Bit, Simultaneous-Sampling ADCs with PGA, Filter, and 8-/12-Bit Dual-Stage DAC

4-Channel, 16-Bit, Simultaneous-Sampling ADCs
with PGA, Filter, and 8-/12-Bit Dual-Stage DAC
CONFIG_ Register (0Ch–0Fh)
BIT 15
X
BIT 14
X
BIT 13
X
BIT 12
BDAC3
BIT 11
BDAC2
BIT 10
BDAC1
BIT 9
BDAC0
BIT 8
DIFF
BIT 7
BIT 6
BIT 5
BIT 4
EQ
MODG1
MODG0
PDPGA
This register sets the input gain of each ADC channel
and selects one of the default filters or EQ function.
X<15:13>: Don’t-care bits.
BDAC3:BDAC0<12:9>: Sets the input bias voltage for
AC-coupled signals when ENBIAS_ is set to 1.
0000 = 33% of AVDD.
0001 = 35% of AVDD.
0010 = 38% of AVDD.
0011 = 40% of AVDD.
0100 = 42% of AVDD.
0101 = 44% of AVDD.
0110 = 46% of AVDD.
0111 = 48% of AVDD.
1000 = 50% of AVDD.
1001 = 52% of AVDD.
1010 = 54% of AVDD.
1011 = 56% of AVDD.
1100 = 58% of AVDD.
1101 = 60% of AVDD.
1110 = 62% of AVDD.
1111 = 65% of AVDD.
DIFF<8>: Input mode select bit.
1 = normal operation in all modes.
0 = use for a 2x input signal range in LP, gain = 1
mode. Note that THD degrades.
BIT 3
BIT 2
BIT 1
BIT 0
FILT
PGAG
ENBIASP
ENBIASN
EQ<7>: EQ function.
1 = analog EQ enabled.
0 = analog EQ disabled (default).
MODG1:MODG0<6:5>: ADC modulator gain.
00 = 1 (default).
01 = 2.
10 = 4.
11 = 4.
PDPGA<4>: PGA power-down control.
1 = PGA powered down, gain = 1.
0 = PGA powered, PGA gain set by PGAG (default).
FILT<3>: Programmable filter select.
1 = use preprogrammed LP filter.
0 = use preprogrammed EQ filter (default).
PGAG<2>: High PGA gain setting.
1 = PGA, gain = 16.
0 = PGA, gain = 8 (default).
ENBIASP<1>: Positive input bias enable. Bias voltage
set by BDAC3:BDAC0.
1 = selfbiasing enabled.
0 = selfbiasing disabled (default).
ENBIASN<0>: Negative input bias enable. Bias volt-
age set by BDAC3:BDAC0.
1 = selfbiasing enabled.
0 = selfbiasing disabled (default).
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