MAX11014 Datasheet, PDF (58/69 Pages) Maxim Integrated Products – Automatic RF MESFET Amplifier Drain-Current Controllers

Automatic RF MESFET Amplifier
Drain-Current Controllers
For a GATE_ voltage alarm condition, GATE_ remains
clamped and ALM_CLMP 10 mode functions the same
as 11 mode. This exception breaks the feedback loop
that would have otherwise been created by sampling the
GATE_ voltage and then clamping that same voltage.
• ALM_CLMP1/ALM_CLMP0 = 11
This mode provides semi-automatic clamping. Prior
to an alarm condition, the GATE_ voltage is controlled
by the sense voltage (MAX11014) or the DAC setting
(MAX11015). When an alarm condition is triggered,
the GATE_ voltage clamps to ACLAMP_. The clamp
holds the GATE_ output in this condition, even if sub-
sequent ADC samples are taken and all ALARM
channels are cleared. To release the clamp, rewrite
the ALM_CLMP1/ALM_CLMP0 bits to 11 or 01.
OPSAFE Inputs
Set the OPSAFE1 and OPSAFE2 inputs high to clamp
the GATE1 and GATE2 outputs to the externally applied
voltage at ACLAMP1 and ACLAMP2, respectively.
OPSAFE1/OPSAFE2 override any software commands.
The ALM_CLMP1/ALM_CLMP0 bits in the hardware
ALARM configuration register also provide clamping
functionality.
SRAM LUTs
The MAX11014/MAX11015 implement four independent
lookup tables (LUTs). The LUTs are temperature based
(TLUT) and numeric based (KLUT). Channel 1 and
channel 2 each have a separate T and K LUT. Each
LUT can store up to 48 separate data words. See
Figure 28. In addition to storing data values, the LUT
memory also contains configuration registers that spec-
ify LUT size, hysteresis bit value, and step size. Table
28 details how the LUTs are configured in memory.
Write data to the LUTs with the following sequence:
1) Write to the LUT address register to set the base
address for the first data word (the LUTWORD bits
are don’t care in LUT writes).
2) Write to the LUT data register to write data values.
Each time the LUT data register is written, the
address in the LUT memory space is automatically
incremented.
Read data from the LUTs with the following sequence:
1) Write to the LUT address register to set the base
address for the first data word and the number of
LUT words to be read.
2) Issue a single read command of the LUT data reg-
ister. The MAX11014/MAX11015 then fill the FIFO
with the requested LUT data, starting with the data
at the LUTADD base address and incrementing
until reaching either the top of memory or the num-
ber of locations based on the LUTWORD code.
3) Read each of the 16-bit LUT data words (including
the 3- or 4-bit channel tag) from the FIFO at DOUT
in SPI mode and SDA in I²C mode.
Begin a LUT write or read command by writing to the
LUT address register. See Table 23. This register sets
the LUT base address and the number of LUT locations
to be read in a subsequent read of the LUT data regis-
ter. Set the command byte to 7Ah to write to the LUT
address register. Set the LUTWORD bits, D15–D8, to
the number of LUT words (1 to 48) to be output during
a LUT read operation. Set the LUTADD bits, D7–D0, to
point to the base address of the LUT data. The
TLUT1-0 to TLUT1-47 (channel 1) values are stored at
addresses 00h to 2Fh. The TLUT2-0 to TLUT2-47
(channel 2) values are stored at addresses 30h to 5Fh.
The KLUT1-0 to KLUT1-47 (channel 1) values are
stored at addresses 60h to 8Fh. The KLUT2-0 to
KLUT2-47 (channel 2) values are stored at addresses
90h to BFh.
The LUTs are defined by setting the following parameters:
1) The table’s base value
2) The step size of the table (how far apart the
entries are)
3) The hysteresis threshold size
4) The size of the LUT (the number of entries)
LUT Configuration
Write a LUT configuration sequence to initialize the step
size, hysteresis threshold size, and size of the LUT.
Determine the respective channel’s temperature or K
LUT configuration with the following sequence:
1) Set the LUTADD bits in the LUT address register to
C0h (TLUT1), C1h (TLUT2), C2h (KLUT1) or C3h
(KLUT2). See Table 28a.
2) Write to the LUT data register (LUTDAT15–LUTDAT0)
to initialize the step size, hysteresis threshold size,
and size of the LUT. See Table 28b.
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