MAX11014 Datasheet, PDF (36/69 Pages) Maxim Integrated Products – Automatic RF MESFET Amplifier Drain-Current Controllers

Automatic RF MESFET Amplifier
Drain-Current Controllers
Table 10a. Maximum GATE_ Voltage Modes
CH_OCM1
0
0
1
1
CH_OCM0
0
1
0
1
FUNCTION
Maximum positive voltage at GATE_ = AGND.
Maximum positive voltage at GATE_ = AGND + 250mV.
Maximum positive voltage at GATE_ = AGND + 500mV.
Maximum positive voltage at GATE_ = AGND + 750mV.
Table 10b. Clock Modes
CKSEL1
0
0
1
1
CKSEL0
0
1
0
1
CONVERSION
CLOCK
Internal
Internal
Reserved
Internal
ACQUISITION/SAMPLING
Internally timed acquisitions and conversions. Default state. Begin a
conversion by writing to the ADC conversion register to convert all
channels specified in this register.
Internally timed acquisitions and conversions. Begin a conversion by
pulling CNVST low only once for at least 20ns to convert all of the
channels selected in the ADC conversion register.
Do not use.
Externally timed single acquisitions. Conversions internally timed.
Begin each individual conversion by pulling CNVST low for each
channel converted. See the Electrical Characteristics table for CNVST
timing. The MAX11014/MAX11015 acquire while CNVST is low and
sample when CNVST returns high.
Table 10c. ADC Reference Modes
ADCREF1
0
1
1
X = Don’t care.
ADCREF0
X
0
1
ADC VOLTAGE REFERENCE
External. Bypass REFADC with a 0.1µF capacitor to AGND.
Internal. Leave REFADC unconnected.
Internal. Bypass REFADC with a 0.1µF capacitor to AGND for better noise performance.
Table 10d. DAC Reference Modes
DACREF1
0
1
1
DACREF0
X
0
1
DAC VOLTAGE REFERENCE
External. Bypass REFDAC with a 0.1µF capacitor to AGND.
Internal. Leave REFDAC unconnected.
Internal. Bypass REFDAC with a 0.1µF capacitor to AGND for better noise performance.
X = Don’t care.
Bits D15–D12 of the software configuration register are
don’t care. Set the LDAC2 bit, D11, to 1 to load the new
value of V_DAC2, upon completion of a V_DAC2(CODE)
calculation, into both the channel 2 DAC input and out-
put registers. See Figure 20. Set to 0 to load the new
value of V_DAC2, upon completion of a V_DAC2(CODE)
calculation, to only the channel 2 DAC input register.
Set the T2COMP1/0 bits, D10 and D9, to control the
channel 2 temperature LUT. See Table 11a. Set the
KSRC2-2/1/0 bits, D8, D7, and D6, to control the chan-
nel 2 K parameter LUT. See Table 11b and the SRAM
LUTs section.
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