MAX11014 Datasheet, PDF (29/69 Pages) Maxim Integrated Products – Automatic RF MESFET Amplifier Drain-Current Controllers

Automatic RF MESFET Amplifier
Drain-Current Controllers
Command Byte/Data Bytes (Read Cycle)
Begin a read cycle by issuing a START condition fol-
lowed by writing a 7-bit address (Figure 18) and a read
bit (R/W = 1). After writing the 8th bit, the
MAX11014/MAX11015 (the slave) issue an acknowl-
edge signal by pulling SDA low for one clock cycle.
Write the command byte to the slave after writing the
slave address (C7–C0, MSB first). See Figures 16, 18,
19, Table 1, and the Command Byte section. Following
the command byte, the slave issues another acknowl-
edge signal, pulling SDA low for one clock cycle. After
writing the command byte, issue a repeated START
condition (Sr), write the slave address byte again, and
write a 9th bit for an acknowledge signal. After a third
acknowledge signal, read out the 2 bytes at SDA. After
reading the first byte, the master should send an
acknowledge (A). After reading the second byte, the
master should send a not-acknowledge (N) followed by
a stop signal.
Default Reads
A standard I²C read command involves writing the
slave address, command byte, slave address byte
again, and then reading the data at SDA. This is
detailed in the 5-byte read cycle sequence in Figure
16. Read from the MAX11014/MAX11015 through the
default read command to avoid writing a command
byte and second slave address byte. See the default
read sequence in Figure 16.
Begin a default read cycle by writing the slave address
byte followed by an acknowledge bit. Read out the next
2 data bytes, with acknowledge bits from the master to
the slave following each byte. Continue to acknowledge
the data by sending acknowledge (A) signals. After
reading the final byte, the master should send a not-
acknowledge (N) followed by a stop signal. The default
read cycle reads out the data from the register (located
in Table 2) of the previously assigned command byte.
See Figure 18. This default read feature is useful for 2-
wire reads to maximize the data throughput without
having the overhead of setting the slave address and
command byte each time.
MASTER TO SLAVE
SLAVE TO MASTER
5-BYTE READ CYCLE
1
7
11
8
1
7
11
8
S
SLAVE
ADDRESS
R A COMMAND BYTE
A Sr
SLAVE
ADDRESS
RA
DATA BYTE
1
8
N
DATA BYTE
MSB DETERMINES
WHETHER TO READ OR WRITE TO
REGISTERS
DEFAULT READ CYCLE
1
7
11
8
1
S
SLAVE
ADDRESS
RA
DATA BYTE
A
8
DATA BYTE
11
N P OR Sr
NUMBER OF BITS
11
N P OR Sr
NUMBER OF BITS
Figure 16. Read Cycle
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