MAX11166 Datasheet, PDF (30/33 Pages) Maxim Integrated Products – 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN

MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
In daisy-chain mode, the maximum conversion rate is
reduced due to the increased readback time. For instance,
with a 6ns or less digital host setup time and 3V interface, up
to four MAX11166/MAX11167 devices running at a conver-
sion rate of 217ksps (MAX11167) or 322ksps (MAX11166)
can be daisy-chained on a 3-wire port.
Layout, Grounding, and Bypassing
For best performance, use PCBs with ground planes.
Ensure that digital and analog signal lines are separated
from each other. Do not run analog and digital lines parallel
to one another (especially clock lines), and avoid running
digital lines underneath the ADC package. A single solid
GND plane configuration with digital signals routed from
one direction and analog signals from the other provides
the best performance. Connect the GND and AGNDS pins
on the MAX11166/MAX11167 to this ground plane. Keep
the ground return to the power-supply low impedance and
as short as possible for noise-free operation.
A 500pF C0G (or NPO) ceramic chip capacitor should
be placed between AIN+ and the ground plane as close
as possible to the MAX11166/MAX11167. This capaci-
tor reduces the inductance seen by the sampling cir-
cuitry and reduces the voltage transient seen by the input
source circuit.
For best performance, connect the REF output to the
ground plane with a 16V, 10FF ceramic chip capacitor
with a X5R or X7R dielectric in a 1210 or smaller case
size. Ensure that all bypass capacitors are connected
directly into the ground plane with an independent via.
Bypass VDD and OVDD to the ground plane with 0.1FF
ceramic chip capacitors on each pin as close as pos-
sible to the device to minimize parasitic inductance.
Add at least one bulk 10FF decoupling capacitor to V_DD
and OVDD per PCB. For best performance, bring a
V_DD power plane in on the analog interface side of the
MAX11166/MAX11167 and a OVDD power plane from the
digital interface side of the device.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on
an actual transfer function from a straight line. For these
devices, this straight line is a line drawn between the end
points of the transfer function, once offset and gain errors
have been nullified.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. For
these devices, the DNL of each digital output code is
measured and the worst-case value is reported in the
Electrical Characteristics table. A DNL error specification
of less than Q1 LSB guarantees no missing codes and a
monotonic transfer function.
Offset Error
For the MAX11166/MAX11167, the offset error is defined
at code center 0x8000. This code center should occur at
0V input between AIN+ and AIN-. The offset error is the
actual voltage required to produce code center 0X8000,
expressed in mV.
Gain Error
Gain error is defined as the difference between the change
in analog input voltage required to produce a top code
transition minus a bottom code transition, subtracted from
the ideal change in analog input voltage on (5.0V/4.096V)
x V_REF x (65534/65536). For the MAX11166/MAX11167,
top code transition is 0xFFFE to 0xFFFF. The bottom
code transition is 0x0000 and 0x0001. For the MAX11166/
MAX11167, the analog input voltage to produce these
code transitions is measured and then the gain error is
computed by subtracting 2.0 x (5.0V/4.096V) x V_REF x
(65534/65536) from this measurement.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quantiza-
tion error (residual error). The ideal, theoretical minimum
analog-to-digital noise is caused by quantization noise
error only and results directly from the ADC’s resolution
(N bits):
SNR = (6.02 x N + 1.76)dB
where N = 16 bits. In reality, there are other noise sources
besides quantization noise: thermal noise, reference
noise, clock jitter, etc. SNR is computed by taking the ratio
of the RMS signal to the RMS noise, which includes all
spectral components not including the fundamental, the
first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:

SINAD(dB=) 20 × log 
Signal_RMS


^{(Noise + Distortion)}_RMS 
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