MAX11166 Datasheet, PDF (28/33 Pages) Maxim Integrated Products – 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN

MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
A rising edge on CNVST completes the acquisition and
initiates the conversion. Once a conversion is initiated, it
continues to completion irrespective of the state of CNVST.
When a conversion is complete, the busy indicator is pre-
sented onto each DOUT and the MAX11166/MAX11167
return to the acquisition phase. The busy indicator for the
last ADC in the chain can be connected to an interrupt input
on the digital host. The digital host should insert a 50ns
delay from the receipt of this interrupt before reading out
data from all ADCs to ensure that all devices in the chain
have completed conversion.
The conversion data is stored within an internal shift reg-
ister. To read these bits out, CNVST is brought low and
each bit is shifted out on subsequent SCLK falling edge.
The DIN input of each ADC in the chain is used to transfer
conversion data from the previous ADC into the internal
shift register of the next ADC, thus allowing for data to be
clocked through the multichip chain on each SCLK falling
edge. The total of number of falling SCLKs needed to read
back all data from N ADCs is 16 × N + 1 edges, the one
additional SCLK falling edge required to clock out the busy
mode bit from the host side ADC.
CNVST
DIN
MAX11166
MAX11167
DOUT
DA
DEVICE A
SCLK
CNVST
DIN
MAX11166
MAX11167
DOUT
DEVICE B
SCLK
CONFIG
CONVERT
DIGITAL HOST
D_B
DATA IN
CLK
Figure 12. Daisy-Chain, No-Busy Indicator Mode Connection Diagram
CNVST
DIN
ACQUISITION
tCONV
CONVERSION
SCLK
DOUTB
tCNVPW
tCYC
1
DB15
tSCLKL
2
3
tDDO
14
tSCLKH
DB14 DB13
tACQ
ACQUISITION
tSCLK
15
16
17
18
DB1 DB0 DA15 DA14
tSSCKCNF
30
31
32
DA1 DA0
Figure 13. Daisy-Chain, No-Busy Indicator Mode Timing
tHSCKCNF
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