MAX11166 Datasheet, PDF(18/33 Page) Maxim Integrated Products – 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN

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MAX11166 Datasheet, PDF (18/33 Pages) Maxim Integrated Products – 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN

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MAX11166/MAX11167

16-Bit, 500ksps/250ksps, Â±5V SAR ADCs

with Internal Reference in TDFN

Overvoltage Input Clamps

The MAX11166/MAX11167 include an input clamping

circuit that activates when the input voltage at AIN+ is

above (VDD + 300mV) or below -(VDD + 300mV). The

clamp circuit remains high impedance while the input sig-

nal is within the range of Q(VDD + 100mV) and draws little

to no current. However, when the input signal exceeds

this range the clamps begin to turn on. Consequently, to

obtain the highest accuracy, ensure that the input voltage

does not exceed the range of Q(VDD + 100mV).

To make use of the input clamps, connect a resistor (RS)

between the AIN+ input and the voltage source to limit the

voltage at the analog input and to ensure the fault current

into the devices does not exceed Q20mA. Note that the

voltage at the AIN+ input pin limits to approximately 7V

during a fault condition so the following equation can be

used to calculate the value of RS:

VFAULT MAX

20mA

where VFAULTMAX is the maximum voltage that the

source produces during a fault condition.

Figure 1 and Figure 2 illustrate the clamp circuit volt-

age current characteristics for a source impedance

RS = 1280I. While the input voltage is within the Q(VDD

+ 300mV) range, no current flows in the input clamps.

Once the input voltage goes beyond this voltage range,

the clamps turn on and limit the voltage at the input pin.

Internal/External Reference

(REFIO) Configuration

The MAX11166/MAX11167 include a standard SPI inter-

face that selects internal or external reference modes of

operation through an input configuration register (see the

Input Configuration Interface section). The MAX11166/

MAX11167 feature an internal bandgap reference circuit

(VREFIO = 4.096V) that is buffered with an internal ref-

erence buffer that drives the REF pin. The MAX11166/

MAX11167 configure register allows four combinations of

reference configuration. These reference mode are:

Reference Mode 00: ADC reference is provided by the

internal bandgap feed out the REFIO pin, noise filtered

with an external capacitor on the REFIO pin, then buff-

ered by the internal reference buffer and decoupled with

an external capacitor on the REF pin. In this mode the

ADC requires no external reference source.

Reference Mode 01: ADC reference is provided external-

ly and feeds into the REFIO pin, buffered with the internal

reference buffer and decoupled with an external capaci-

tor on the REF pin. This mode is typically used when a

common reference source is needed for more than one

MAX11166/MAX11167.

Reference Mode 10: The internal bandgap is used as

a reference source output and feed out the REFIO pin.

However, the internal reference buffer is in a shutdown

state and the REF pin is high impedance. This state

would typically be used to provide a common reference

source to a set of external reference buffers for several

MAX11166/MAX11167.

MAX11166/MAX11167 INPUT CLAMP

CHARACTERISTICS

AIN+ PIN

INPUT SOURCE

-5

-10

-15

-20

RS = 1280I

VDD = 5.0V

-25

-40 -30 -20 -10 0 10 20 30 40

SIGNAL VOLTAGE AT SOURCE AND AIN+ INPUT (V)

Figure 1. Input Clamp Characteristics