MAX11166 Datasheet, PDF (23/33 Pages) Maxim Integrated Products – 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN

MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
In all interface modes, it is recommended that the SCLK be
idled low to avoid triggering an input configuration write on
the falling edge of CNVST. If at anytime the device detects
a high SCLK state on a falling edge of CNVST, it will enter
the input configuration write mode and will write the state
of DIN on the next 8 falling SCLK edges to the input con-
figuration register.
In all interface modes, all data bits from a previous conver-
sion must be read before reading bits from a new conver-
sion. When reading out conversion data, if too few SCLK
falling edges are provided and all data bits are not read out,
only the remaining unread data bits will be outputted during
the next readout cycle. In such an event, the output data
in every other readout cycle will appear to have been trun-
cated as only the leftover bits from the previous readout
cycle are outputted. This is an indication to the user that
there are insufficient SCLK falling edges in a given readout
cycle. Table 5 provides a guide to aid in the selection of the
appropriate output interface mode for a given application.
CS No-Busy Indicator Mode
The CS no-busy indicator mode is ideally suited for maxi-
mum throughput when a single MAX11166/MAX11167 is
connected to a SPI-compatible digital host. The connec-
tion diagram is shown in Figure 6, and the corresponding
timing is provided in Figure 7.
A rising edge on CNVST completes the acquisition, initi-
ates the conversion, and forces DOUT to high impedance.
The conversion continues to completion irrespective of the
state of CNVST allowing CNVST to be used as a select line
for other devices on the board. If CNVST is brought low
during a conversion and held low throughout the maximum
conversion time, the MSB will be output at the end of the
conversion.
When the conversion is complete, the MAX11166/
MAX11167 enter the acquisition phase. Drive CNVST
low to output the MSB onto DOUT. The remaining data
bits are then clocked by subsequent SCLK falling edges.
DOUT returns to high impedance after the 16th SCLK fall-
ing edge, or when CNVST goes high.
Table 5. ADC Output Interface Mode
Selector Guide
MODE
CS Mode,
No-Busy
Indicator
CS Mode,
With Busy
Indicator
TYPICAL APPLICATION AND BENEFITS
Single or multiple ADCs connected to SPI-
compatible digital host. Ideally suited for
maximum throughput.
Single ADC connected to SPI-compatible
digital host with interrupt input. Ideally suited
for maximum throughput.
Daisy-Chain
Mode,
No-Busy
Indicator
Multiple ADCs connected to a SPI-
compatible digital host. Ideally suited for
multichannel simultaneous sampled isolated
applications.
Daisy-Chain
Mode,
With Busy
Indicator
Multiple ADCs connected to a SPI-
compatible digital host with interrupt input.
Ideally suited for multichannel simultaneous
sampled isolated applications.
CNVST
DOUT
MAX11166
MAX11167 _DIN
SCLK
CONVERT
DIGITAL HOST
DATA IN
CONFIG
CLK
Figure 6. CS No-Busy Indicator Mode Connection Diagram
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