MAX11166 Datasheet, PDF (25/33 Pages) Maxim Integrated Products – 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN

MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
CNVST
tCNVPW
tCYC
DIN
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSSCKCNF
SCLK
tSCLK
tHSCKCNF
tSCLKL
1
2
3
4
15
16
17
tSCLKH
tDDO
tDIS
DOUT
BUSY BIT
D15
D14
D13
D1
D0
Figure 9. CS With Busy Indicator Mode Timing
When the conversion is complete, DOUT transitions from
high impedance to a low logic level, signaling to the digital
host through the interrupt input that data readback can
commence. The MAX11166/MAX11167 then enter the
acquisition phase. The data bits are then clocked out,
MSB first, by subsequent SCLK falling edges. DOUT
returns to high impedance after the 17th SCLK falling
edge or when CNVST goes high, and is then pulled to
OVDD through the external pullup resistor.
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