MAX11166 Datasheet, PDF (21/33 Pages) Maxim Integrated Products – 16-Bit, 500ksps/250ksps, ±5V SAR ADCs with Internal Reference in TDFN

MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Input Configuration Interface
An SPI interface clocked at up to 50MHz controls the
MAX11166/MAX11167. Input configuration data is clocked
into the configuration register on the falling edge of SCLK
through the DIN pin. The data on DIN is used to program
the ADC configuration register. The construct of this reg-
ister is illustrated in Table 4. The configuration register
defines the output interface mode, the reference mode,
and the power-down state of the MAX11166/MAX11167.
Table 4. ADC Configuration Register
Configuring in CS Mode
Figure 4 details the timing for loading the input configuration
register when the MAX11166/MAX11167 are connected in
CS mode (see Figure 6 and Figure 8 for hardware connec-
tions). The load process is enabled on the falling edge of
CNVST when SCLK is held high. The configuration data is
clocked into the configuration register through DIN on the
next 8 SCLK falling edges. Pull CNVST high to complete
the input configuration register load process. DIN should
idle high outside an input configuration register read.
BIT NAME
BIT
DEFAULT
STATE
LOGIC
STATE
FUNCTION
00
CS Mode, No-Busy Indicator
MODE
7:6
00
01
CS Mode, with Busy Indicator
10
Daisy-Chain Mode, No-Busy Indicator
11
Daisy-Chain Mode, with Busy Indicator
00
Reference Mode 0. Internal reference and reference buffer are both
powered on.
REF
5:4
00
01
Reference Mode 1. Internal reference is turned off, but internal reference
buffer powered on. Apply the external reference voltage at REFIO.
Reference Mode 2. Internal reference is powered on, but the internal
10
reference buffer is powered off. This mode allows for internal reference to
be used with an external reference buffer.
11
Reference Mode 3. Internal reference and reference buffer are both
powered off. Apply an external reference voltage at REF.
SHDN
3
0
Reserved
2:0
0
0
Normal Mode. All circuitry is fully powered up at all times.
1
Static Shutdown. All circuitry is powered down.
0
Reserved, Set to 0
CNVST
SCLK
DIN
tHSCKCNF
tSSCKCNF
0
1
2
3
4
5
6
7
tHDINSCK
tSDINSCK
B7
B6
B5
B4
B3
B2
B1
B0
Figure 4. Input Configuration Timing in CS Mode
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