LTC3869-2_15 Datasheet, PDF (8/42 Pages) Linear Technology – Dual, 2-Phase Synchronous Step-Down DC/DC Controllers

LTC3869/LTC3869-2
Typical Performance Characteristics T_A = 25°C, unless otherwise noted.
Shutdown Current
vs Input Voltage
60
50
40
30
20
10
0
5 10 15 20 25 30 35 40
INPUT VOLTAGE (V)
3869 G23
Shutdown Current
vs Temperature
45
40
35
30
25
20
15
10
5
0
–50 –25
0 25 50 75
TEMPERATURE (°C)
100 125
3869 G24
Quiescent Current
vs Input Voltage without EXTV_CC
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
5
10 15 20 25 30 35 40
INPUT VOLTAGE (V)
3869 G25
Pin Functions (UFD/GN)
RUN1, RUN2 (Pin 27, Pin 10/Pin 1, Pin 13): Run Control
Inputs. A voltage above 1.2V on either pin turns on the IC.
However, forcing either of these pins below 1.2V causes
the IC to shut down the circuitry required for that particular
channel. There are 1µA pull-up currents for these pins.
Once the RUN pin raises above 1.2V, an additional 4.5µA
pull-up current is added to the pin.
V_FB1, V_FB2 (Pin 4, Pin 5/Pin 4, Pin 10): Error Amplifier
Feedback Inputs. These pins receive the remotely sensed
feedback voltages for each channel from external resistive
dividers across the outputs.
I_TH1, I_TH2 (Pin 3, Pin 6/Pin 6, Pin 8): Current Control
Thresholds and Error Amplifier Compensation Points.
Each associated channels’ current comparator tripping
threshold increases with its I_TH control voltage.
SGND (Pin 29/Pin 7): Signal Ground. All small-signal
components and compensation components should con-
nect to this ground, which in turn connects to PGND at
one point. Pin 29 is the exposed pad, only available for
the UFD package. The exposed pad must be soldered to
PCB ground for electrical connection and rated thermal
performance.
TK/SS1, TK/SS2 (Pin 2, Pin 7/Pin 5, Pin 9): Output Volt-
age Tracking and Soft-Start Inputs. When one particular
channel is configured to be the master of two channels,
a capacitor to ground at this pin sets the ramp rate for
the master channel’s output voltage. When the channel
is configured to be the slave of two channels, the V_FB
voltage of the master channel is reproduced by a resistor
divider and applied to this pin. Internal soft-start currents
of 1.2µA are charging these pins.
MODE/PLLIN (Pin 25/Pin 27): Forced Continuous Mode,
Burst Mode Operation, or Pulse-Skipping Mode Selection
Pin and External Synchronization Input to Phase Detec-
tor Pin. Connect this pin to SGND to force both channels
in continuous mode of operation. Connect to INTV_CC to
enable pulse-skipping mode of operation. Leave the pin
floating will enable Burst Mode operation. A clock on
the pin will force the controller into continuous mode of
operation and synchronize the internal oscillator with the
clock on this pin. The PLL compensation components are
integrated inside the IC.
38692fa
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