LTC3869-2_15 Datasheet, PDF (24/42 Pages) Linear Technology – Dual, 2-Phase Synchronous Step-Down DC/DC Controllers

LTC3869/LTC3869-2
Applications Information
Phase-Locked Loop and Frequency Synchronization
900
The LTC3869 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (V_CO) and a phase
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The turn-on
of controller 2’s top MOSFET is thus 180 degrees out-
of-phase with the external clock. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the internal filter
network. There is a precision 10µA of current flowing out
of FREQ pin. This allows the user to use a single resistor
to SGND to set the switching frequency when no external
clock is applied to the MODE/PLLIN pin. The internal switch
between FREQ pin and the integrated PLL filter network
is ON, allowing the filter network to be pre-charged to the
same voltage potential as the FREQ pin. The relationship
between the voltage on the FREQ pin and the operating
frequency is shown in Figure 9 and specified in the Electri-
cal Characteristics table. If an external clock is detected on
the MODE/PLLIN pin, the internal switch mentioned above
will turn off and isolate the influence of FREQ pin. Note
that the LTC3869 can only be synchronized to an external
clock whose frequency is within range of the LTC3869’s
internal V_CO. This is guaranteed to be between 250kHz and
780kHz. A simplified block diagram is shown in Figure 10.
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f_OSC, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than f_OSC, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor holds the voltage.
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2 2.5
FREQ PIN VOLTAGE (V)
3869 F09
Figure 9. Relationship Between Oscillator
Frequency and Voltage at the FREQ Pin
2.4V 5V
10µA
R_SET
EXTERNAL
OSCILLATOR
MODE/
PLLIN
DIGITAL
PHASE/ SYNC
FREQUENCY
DETECTOR
FREQ
VCO
3869 F10
Figure 10. Phase-Locked Loop Block Diagram
Typically, the external clock (on MODE/PLLIN pin)
input high threshold is 1.6V, while the input low threshold
is 1V. It is not recommended to apply the external clock
when IC is in shutdown.
Minimum On-Time Considerations
Minimum on-time t_ON(MIN) is the smallest time duration
that the LTC3869 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
t_ON(MIN)
<
V_OUT
V_IN(ƒ)
38692fa
24
For more information www.linear.com/LTC3869