LTC3869-2_15 Datasheet, PDF (23/42 Pages) Linear Technology – Dual, 2-Phase Synchronous Step-Down DC/DC Controllers

LTC3869/LTC3869-2
Applications Information
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may be paralleled to meet
size or height requirements in the design. Due to the high
operating frequency of the LTC3869, ceramic capacitors
can also be used for C_IN. Always consult the manufacturer
if there is any question.
The benefit of the LTC3869 2-phase operation can be
calculated by using the equation above for the higher
power controller and then calculating the loss that would
have resulted if both controller channels switched on at
the same time. The total RMS power lost is lower when
both controllers are operating due to the reduced overlap
of current pulses required through the input capacitor’s
ESR. This is why the input capacitor’s requirement cal-
culated above for the worst-case controller is adequate
for the dual controller design. Also, the input protection
fuse resistance, battery resistance, and PC board trace
resistance losses are also reduced due to the reduced
peak currents in a 2-phase system. The overall benefit of
a multiphase design will only be fully realized when the
source impedance of the power supply/battery is included
in the efficiency testing. The sources of the top MOSFETs
should be placed within 1cm of each other and share a
common C_IN(s). Separating the sources and C_IN may pro-
duce undesirable voltage and current resonances at V_IN.
A small (0.1µF to 1µF) bypass capacitor between the chip
V_IN pin and ground, placed close to the LTC3869, is also
suggested. A 2.2Ω to 10Ω resistor placed between C_IN
(C1) and the V_IN pin provides further isolation between
the two channels.
The selection of C_OUT is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfied, the capacitance is adequate for filtering. The
output ripple (∆V_OUT) is approximated by:
∆V_OUT
≈ I_RIPPLE
⎛
⎜ESR +
⎝
1
8fC_OUT
⎞
⎟
⎠
Setting Output Voltage
The LTC3869 output voltages are each set by an external
feedback resistive divider carefully placed across the out-
put, as shown in Figure 8. The regulated output voltage
is determined by:
V_OUT
=
0.6V
⎛
• _⎜1+
⎝
R_B
R_A
⎞
⎟
⎠
To improve the frequency response, a feed-forward ca-
pacitor, C_FF, may be used. Great care should be taken to
route the V_FB line away from noise sources, such as the
inductor or the SW line.
V_OUT
1/2 LTC3869
V_FB
R_B
C_FF
R_A
3869 F08
Figure 8. Setting Output Voltage
Fault Conditions: Current Limit and Current Foldback
The LTC3869 includes current foldback to help limit load
current when the output is shorted to ground. If the out-
put falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from its
maximum programmed value to one-third of the maximum
value. Foldback current limiting is disabled during the
soft-start or tracking up. Under short-circuit conditions
with very low duty cycles, the LTC3869 will begin cycle
skipping in order to limit the short-circuit current. In this
situation the bottom MOSFET will be dissipating most of
the power but less than in normal operation. The short-
circuit ripple current is determined by the minimum on-
time t_ON(MIN) of the LTC3869 (≈ 90ns), the input voltage
and inductor value:
∆I_L(SC)
=
t_ON(MIN)
•
V_IN
L
where f is the operating frequency, C_OUT is the output
capacitance and I_RIPPLE is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since I_RIPPLE increases with input voltage.
The resulting short-circuit current is:
I_SC
=
1/3
V_{SENSE(MAX )}
R_SENSE
–
1
2
∆I_L(SC)
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