LTC3869-2_15 Datasheet, PDF (13/42 Pages) Linear Technology – Dual, 2-Phase Synchronous Step-Down DC/DC Controllers

LTC3869/LTC3869-2
Operation
The PLL loop filter network is integrated inside the
LTC3869. The phase-locked loop is capable of locking
any frequency within the range of 250kHz to 780kHz. The
frequency setting resistor should always be present to set
the controller’s initial switching frequency before locking
to the external clock.
Power Good (PGOOD Pin)
When V_FB pin voltage is not within ±10% of the 0.6V
reference voltage, the PGOOD pin is pulled low. The
PGOOD pin is also pulled low when the RUN pin is below
1.2V or when the LTC3869 is in the soft-start or tracking
phase. The PGOOD pin will flag power good immediately
when both V_FB pins are within the ±10% of the reference
window. However, there is an internal 20µs power bad
mask when V_FB goes out the ±10% window. The PGOOD
pin is allowed to be pulled up by an external resistor to a
source of up to 6V.
Output Overvoltage Protection
An overvoltage comparator, OV, guards against transient
overshoots (>10%) as well as other more serious condi-
tions that may overvoltage the output. In such cases, the
top MOSFET is turned off and the bottom MOSFET is turned
on until the overvoltage condition is cleared.
For more information www.linear.com/LTC3869
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