LTC3869-2_15 Datasheet, PDF (18/42 Pages) Linear Technology – Dual, 2-Phase Synchronous Step-Down DC/DC Controllers

LTC3869/LTC3869-2
Applications Information
duty cycles up to the maximum of 95%, use the following
equation to find the minimum inductance.
L _MIN
>
f_SW
V_OUT
• I_LOAD(MAX)
•
1.4
where
L_MIN is in units of µH
f_SW is in units of MHz
Inductor Core Selection
Once the inductance value is determined, the type of in-
ductor must be selected. Core loss is independent of core
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Power MOSFET and Schottky Diode
(Optional) Selection
Two external power MOSFETs must be selected for each
controller in the LTC3869: one N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTV_CC
voltage. This voltage is typically 5V during start-up
(see EXTV_CC Pin Connection). Consequently, logic-level
threshold MOSFETs must be used in most applications.
The only exception is if low input voltage is expected (V_IN
< 5V); then, sub-logic level threshold MOSFETs (V_GS(TH)
< 3V) should be used. Pay close attention to the BV_DSS
specification for the MOSFETs as well; most of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the
on-resistance R_DS(ON), Miller capacitance C_MILLER, input
voltage and maximum output current. Miller capacitance,
C_MILLER, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. C_MILLER is equal to the increase in gate charge
along the horizontal axis while the curve is approximately
flat divided by the specified change in V_DS. This result is
then multiplied by the ratio of the application applied V_DS
to the gate charge curve specified V_DS. When the IC is
operating in continuous mode the duty cycles for the top
and bottom MOSFETs are given by:
Main Switch Duty Cycle = ^VOUT
V_IN
Synchronous Switch Duty Cycle = ^{VIN – VOUT}
V_IN
The MOSFET power dissipations at maximum output
current are given by:
P_MAIN
=
V_OUT
V_IN
(^I_MAX )² (^{1+ d})^R_DS(ON) ⁺
(^V_IN )^{2 ⎛⎝⎜IM}₂^{AX ⎞⎠⎟}(^R_DR )(^C_MILLER ) ^•
⎡
⎢
⎣⎢
V_INTVCC
1
– V_TH(MIN)
+
1
V_TH(MIN)
⎤²
⎥
⎦⎥
•
f_OSC
P_SYNC
=
V_IN
– V_OUT
V_IN
(^I_MAX
)²
(^{1+ d})^R_DS(ON)
where d is the temperature dependency of R_DS(ON) and
R_DR (approximately 2Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. V_TH(MIN) is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I²R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V_IN < 20V
the high current efficiency generally improves with larger
MOSFETs, while for V_IN > 20V the transition losses rapidly
increase to the point that the use of a higher R_DS(ON) device
with lower C_MILLER actually provides higher efficiency.
The synchronous MOSFET losses are greatest at high input
18
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