LTC3738 Datasheet, PDF (8/32 Pages) Linear Technology – 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning

LTC3738
PI FU CTIO S
FCB/SYNC (Pin 1): Forced Continuous Control Input. The
voltage applied to this pin sets the operating mode of the
controller. The forced continuous current mode is active
when the applied voltage is less than 0.6V. Pulse skip
mode operation will be active when the pin is allowed to
float and Stage Shedding mode will be active if the pin is
tied to the V_CC pin. When an external clock is present, the
controller will be synchronized to the external clock and
forced continuous mode is selected internally. (Do not
apply voltage to this pin prior to the application of voltage
on the V_CC pin.)
PLLFLTR (Pin 2): The phase-locked loop’s lowpass filter
is tied to this pin. Alternatively, this pin can be driven with
an AC or DC voltage source to vary the frequency of the
internal oscillator. (Do not apply voltage to this pin prior to
the application of voltage on the V_CC pin.)
IN⁺, IN^– (Pins 4, 3): Inputs to a Precision, Unity-Gain
Differential Amplifier with Internal Precision Resistors.
This provides true remote sensing of both the positive and
negative load terminals for precise output voltage control.
AVP (Pin 5): Active Voltage Positioning Load Slope Pro-
gramming Pin. A resistor tied between this pin and IN⁺
sets the load slope.
EAIN (Pin 6): This is the input to the error amplifier which
compares the VID divided feedback voltage to the internal
0.6V reference voltage.
SENSE1⁺, SENSE2⁺, SENSE3⁺, SENSE1^–, SENSE2^–,
SENSE3^– (Pins 7 to 12): The Inputs to Each Differential
Current Comparator. The I_TH pin voltage and built-in
offsets between the SENSE^– and SENSE⁺ pins, in conjunc-
tion with R_SENSE, set the current trip threshold level.
SS (Pin 13): Combination of Soft-Start and Short-Circuit
Detection Timer. A capacitor to ground at this pin sets the
ramp time to full current output as well as the time delay
prior to an output voltage short-circuit shutdown.
I_TH (Pin 14): Error Amplifier Output and Switching Regu-
lator Compensation Point. All three current comparator’s
thresholds increase with this control voltage.
TSNS (Pin 15): This pin selects external or internal ther-
mal detection. Tying this pin to V_CC will enable the internal
thermal detector. When the voltage at this pin is less than
V_CC – 1.6V, the internal thermal detector is disabled and
this pin serves as the input to an internal comparator
which is referenced to V_CC/3.
VR_HOTB (Pin 16): This open-collector output is pulled
low when voltage at the TSNS pin is less than V_CC/3. If
TSNS is tied to V_CC, this pin is pulled low when the internal
thermal detector is tripped.
PGND (Pin 24): Driver Power Ground. This pin connects
to the sources of the bottom N-channel external MOSFETs
and the (–) terminals of C_IN.
BG1, BG2, BG3 (Pins 25, 23, 22): High Current Gate
Drives for the Bottom N-Channel MOSFETs. Voltage swing
at these pins is from ground to V_CC.
V_CC (Pin 26): Main Supply Pin. Because this pin supplies
both the controller circuit power as well as the high power
pulses supplied to drive the external MOSFET gates, this
pin needs to be very carefully and closely decoupled to the
IC’s PGND pin.
3738f
8