LTC3738 Datasheet, PDF (14/32 Pages) Linear Technology – 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning

LTC3738
APPLICATIO S I FOR ATIO
The basic application circuit is shown on the first page of
this data sheet. External component selection is driven by
the load requirement, and normally begins with the selec-
tion of an inductance value based upon the desired
operating frequency, inductor current and output voltage
ripple requirements. Once the inductors and operating
frequency have been chosen, the current sensing resis-
tors can be calculated. Next, the power MOSFETs and
Schottky diodes are selected. Finally, C_IN and C_OUT are
selected according to the required voltage ripple require-
ments. The circuit shown on the first page of this data
sheet can be configured for operation up to a MOSFET
supply voltage of 28V (limited by the external MOSFETs).
Operating Frequency
The IC uses a constant frequency architecture with the
frequency determined by an internal capacitor. This ca-
pacitor is charged by a fixed current plus an additional
current which is proportional to the voltage applied to the
PLLFLTR pin. Refer to the Phase-Locked Loop and Fre-
quency Synchronization and Setup sections for additional
information.
A graph for the voltage applied to the PLLFLTR pin versus
frequency is given in Figure 2. As the operating frequency
is increased the gate charge losses will be higher, reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 530kHz.
550
450
350
250
150
0
0.5 1.0 1.5 2.0 2.5
PLLFLTR PIN VOLTAGE (V)
3738 F02
Figure 2. Operating Frequency vs V_PLLFLTR
Inductor Value Calculation and Output Ripple Current
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge and transition losses. In addition to
this basic tradeoff, the effect of inductor value on ripple
current and low current operation must also be consid-
ered. The PolyPhase approach reduces both input and
output ripple currents while optimizing individual output
stages to run at a lower fundamental frequency, enhancing
efficiency.
The inductor value has a direct effect on ripple current. The
inductor ripple current ∆I_L per individual section, N,
decreases with higher inductance or frequency and in-
creases with higher V_IN or V_OUT:
∆I_L
=
V_OUT
fL
⎛⎝⎜_1−
V_OUT
V_IN
⎞
⎠⎟
where f is the individual output stage operating frequency.
In a PolyPhase converter, the net ripple current seen by the
output capacitor is much smaller than the individual
inductor ripple currents due to the ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.
Figure 3 shows the net ripple current seen by the output
capacitors for the different phase configurations. The
output ripple current is plotted for a fixed output voltage as
the duty factor is varied between 10% and 90% on the
x-axis. The output ripple current is normalized against the
inductor ripple current at zero duty factor. The graph can
be used in place of tedious calculations. As shown in
Figure 3, the zero output ripple current is obtained when:
V_{OUT =} k _{where k = 1, 2, ..., N – 1}
V_IN N
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