LTC3738 Datasheet, PDF (11/32 Pages) Linear Technology – 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning

U
OPERATIO (Refer to Functional Diagram)
Main Control Loop
The IC uses a constant frequency, current mode step-
down architecture. During normal operation, each top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator, I₁, resets each RS latch. The peak inductor
current at which I₁ resets the RS latch is controlled by the
voltage on the I_TH pin, which is the output of the error
amplifier EA. The EAIN pin receives a portion of the voltage
feedback signal via the differential amplifier through the
internal VID DAC and is compared to the internal reference
voltage. When the load current increases, it causes a slight
decrease in the EAIN pin voltage relative to the 0.6V
reference, which in turn causes the I_TH voltage to increase
until each inductor’s average current matches one third of
the new load current (assuming all three current sensing
resistors are equal). In pulse skip mode and Stage Shed-
ding mode, after each top MOSFET has turned off, the
bottom MOSFET is turned on until either the inductor
current starts to reverse, as indicated by current compara-
tor I₂, or the beginning of the next cycle.
The top MOSFET drivers are biased from floating boot-
strap capacitor C_B, which is normally recharged during
each off cycle through an external Schottky diode. When
V_IN decreases to a voltage close to V_OUT, however, the
loop may enter dropout and attempt to turn on the top
MOSFET continuously. The dropout detector counts the
number of oscillator cycles that the bottom MOSFET
remains off and periodically forces a brief on period to
allow C_B to recharge.
The main control loop is shut down by pulling the OUTEN
pin low. Pulling up OUTEN allows an internal 1.5µA current
source to charge soft-start capacitor C_SS at the SS pin. The
internal I_TH voltage is clamped to the SS voltage while C_SS
is slowly charged up. This “soft-start” clamping prevents
abrupt current from being drawn from the input power
source. When the OUTEN pin is low, all functions are kept
in a controlled state.
LTC3738
Low Current Operation
The FCB/SYNC pin is a multifunction pin: 1) a logic input
to select between three modes of operation and 2) external
clock input pin for synchronization.
When the FCB/SYNC pin voltage is below 0.6V, the
controller performs as a continuous, PWM current mode
synchronous switching regulator. The top and bottom
MOSFETs are alternately turned on to maintain the output
voltage independent of direction of inductor current.
When the FCB/SYNC pin is below V_CC – 1.5V, but greater
than 0.6V, the controller performs as a pulse skip mode
switching regulator. Pulse skip mode operation turns off
the synchronous MOSFET(s) when the inductor current
goes negative. Switching cycles will be skipped when the
output load current drops below 3% of the maximum
designed load current in order to maintain the output
voltage. Pulse skip operation provides low noise, constant
frequency operation at light load conditions.
When the FCB/SYNC pin is tied to the V_CC pin, Stage
Shedding mode is enabled. This mode provides constant
frequency, discontinuous current operation over the wid-
est possible output current range. At approximately 10%
of maximum designed load current, the second and third
output stages are shut off and the first controller alone is
active in discontinuous current mode. This “stage shed-
ding” optimizes efficiency by eliminating the gate charging
losses and switching losses of the other two output
stages. Additional cycles will be skipped when the output
load current drops below 1% of maximum designed load
current in order to maintain the output voltage. This
constant frequency operation is more efficient than pulse
skip mode operation at very light load conditions.
3738f
11