LTC3738 Datasheet, PDF (12/32 Pages) Linear Technology – 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning

LTC3738
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OPERATIO (Refer to Functional Diagram)
Tying the FCB/SYNC pin to ground will force continuous
current operation. This is the least efficient operating
mode, but may be desirable in certain applications. The
output can source or sink current in this mode. When
forcing continuous operation and sinking current, this
current will be forced back into the main power supply,
potentially boosting the input supply to dangerous volt-
age levels.
Feeding a clock signal into the FCB/SYNC pin will syn-
chronize the LTC3738 to the external clock. See Fre-
quency Synchronization or Setup for more information.
Frequency Synchronization or Setup
The phase-locked loop allows the internal oscillator to be
synchronized to an external source using the FCB/SYNC
pin. The output of the phase detector at the PLLFLTR pin
is also the DC frequency control input of the oscillator
which operates over a 210kHz to 530kHz range corre-
sponding to a voltage input from 0V to 2.4V. When locked,
the PLL aligns the turn on of the top MOSFET to the rising
edge of the synchronizing signal and forced continuous
mode is set internally. When no frequency information is
supplied to the FCB/SYNC pin, PLLFLTR goes low, forcing
the oscillator to minimum frequency. A DC source can be
applied to the PLLFLTR pin to externally set the desired
operating frequency.
Differential Amplifier
This amplifier provides true differential output voltage
sensing. Sensing both V_OUT+ and V_OUT– benefits regula-
tion in high current applications and/or applications hav-
ing electrical interconnection losses. This sensing also
isolates the physical power ground from the physical
signal ground preventing the possibility of troublesome
“ground loops” on the PC layout and prevents voltage
errors caused by board-to-board interconnects, particu-
larly helpful in VRM designs.
Power Good
The PGOOD pin is connected to the drain of an internal
MOSFET. The MOSFET is turned on when the output
voltage exceeds the PGOOD ±10% tolerance window. The
PGOOD signal is blanked for approximately 100µs during
VID transitions. If a new VID transition occurs before the
previous blanking time expires, the timer is reset.
Short-Circuit Detection
The SS capacitor is used initially to limit the inrush current
from the input power source. Once the controllers have
been given time, as determined by the capacitor on the SS
pin, to charge up the output capacitors and provide full
load current, the SS capacitor is then used as a short-
circuit timeout circuit. If the output voltage falls to less
than 62.5% of its nominal output voltage, the SS capacitor
begins discharging, assuming that the output is in a severe
overcurrent and/or short-circuit condition. If the condition
lasts for a long enough period, as determined by the size
of the SS capacitor, the controller will be shut down until
the OUTEN pin voltage is recycled. This built-in latchoff
can be overridden by providing >5µA at a compliance of 4V
to the SS pin. This current shortens the soft-start period
but prevents net discharge of the SS capacitor during a
severe overcurrent and/or short-circuit condition. Foldback
current limiting is activated when the output voltage falls
below 62.5% of its nominal level whether or not the short-
circuit latchoff circuit is enabled. Foldback current limit
can be overridden by clamping the EAIN pin such that the
voltage is held above the (62.5%)(0.6V) or 0.375V level
even when the actual output voltage is low.
The SS capacitor will be reset if the input voltage, (V_CC) is
allowed to fall below approximately 4V. The capacitor on
the pin will be discharged until the short-circuit arming
latch is disarmed. The SS capacitor will attempt to cycle
through a normal soft-start ramp up after the V_CC supply
rises above 4V. This circuit prevents power supply latchoff
in the event of input power switching break-before-make
situations.
3738f
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