LTC3738 Datasheet, PDF (23/32 Pages) Linear Technology – 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning

LTC3738
APPLICATIO S I FOR ATIO
Undervoltage Reset
In the event that the input power source to the IC (V_CC)
drops below 4V, the SS capacitor will be discharged to
ground and the controller will be shut down. When V_CC
rises above 4V, the SS capacitor will be allowed to re-
charge and initiate another soft-start turn-on attempt. This
may be useful in applications that switch between two
supplies that are not diode connected, but note that this
cannot make up for the resultant interruption of the
regulated output.
Phase-Locked Loop and Frequency Synchronization
The IC has a phase-locked loop comprised of an internal
voltage controlled oscillator and phase detector. This
allows the top MOSFET of output stage 1’s turn-on to be
locked to the rising edge of an external source. The
frequency range of the voltage controlled oscillator is
±50% around the center frequency f_O. A voltage applied to
the PLLFLTR pin of 1.2V corresponds to a frequency of
approximately 350kHz. The nominal operating frequency
range of the IC is 210kHz to 530kHz.
The phase detector used is an edge sensitive digital type
that provides zero degrees phase shift between the
external and internal oscillators. This type of phase
detector will not lock the internal oscillator to harmonics
of the input frequency. The PLL hold-in range, ∆f_H, is
equal to the capture range, ∆f_C:
∆f_H = ∆f_C = ±0.5 f_O
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter components on the PLLFLTR pin. A simplified block
diagram is shown in Figure 8.
If the external frequency (f_PLLIN) is greater than the oscil-
lator frequency, f_OSC, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than f_OSC, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal fre-
quencies are the same, but exhibit a phase difference, the
current sources turn on for an amount of time correspond-
ing to the phase difference. Thus, the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
PHASE
2.4V
DETECTOR/
OSCILLATOR
EXTERNAL
OSC
FCB/SYNC
DIGITAL
PHASE/
FREQUENCY
DETECTOR
R_LP
10k
C_LP
PLLFLTR
OSC
3738 F08
Figure 8. Phase-Locked Loop Block Diagram
stable operating point, the phase comparator output is
open and the filter capacitor C_LP holds the voltage. The IC
FCB/SYNC pin must be driven from a low impedance
source such as a logic gate located close to the pin. When
using multiple ICs for a phase-locked system, the PLLFLTR
pin of the master oscillator should be biased at a voltage
that will guarantee the slave oscillator(s) ability to lock
onto the master’s frequency. A voltage of 1.7V or below
applied to the master oscillator’s PLLFLTR pin is recom-
mended in order to meet this requirement. The resultant
operating frequency will be approximately 500kHz for
1.7V.
The loop filter components (C_LP, R_LP) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C_LP and R_LP determine how fast the loop
acquires lock. Typically R_LP =10k and C_LP ranges from
0.01µF to 0.1µF.
Minimum On-Time Considerations
Minimum on-time, t_ON(MIN), is the smallest time duration
that the IC is capable of turning on the top MOSFET. It is
determined by internal timing delays and the gate charge
of the top MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
t_ON(MIN)
<
V_OUT
V_IN(f₎
3738f
23