LTC3738 Datasheet, PDF (16/32 Pages) Linear Technology – 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning

LTC3738
APPLICATIO S I FOR ATIO
MILLER EFFECT
V_GS
a
b
Q_IN
C_MILLER = (Q_B – Q_A)/V_DS
V
V_GS
V_IN
V_DS
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Figure 4. Gate Charge Characteristic
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gate-
to-drain capacitance. The flat portion of the curve is the
result of the Miller capacitance effect of the drain-to-
source capacitance as the drain drops the voltage across
the current source load. The upper sloping line is due to
the drain-to-gate accumulation capacitance and the gate-
to-source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given V_DS drain voltage, but can be
adjusted for different V_DS voltages by multiplying by the
ratio of the application V_DS to the curve specified V_DS
values. A way to estimate the C_MILLER term is to take the
change in gate charge from points a and b on a manufac-
turers data sheet and divide by the stated V_DS voltage
specified. C_MILLER is the most important selection criteria
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C_RSS
and C_OS are specified sometimes but definitions of these
parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
Main
Switch Duty
Cycle
=
V_OUT
V_IN
Synchronous
Switch
Duty
Cycle
=
⎛
⎝⎜
V_IN
– V_OUT
V_IN
⎞
⎠⎟
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
( ) ^P_MAIN
=
V_OUT
V_IN
⎛⎝⎜
I_MAX
N
⎞⎠⎟
2
1+ δ
R_DS(ON)
+
V_IN2
I_MAX
2N
(^R_DR
)(^C_MILLER
)
•
( ) ^⎡
⎢
⎣⎢
V_CC
–
1
V_TH(MIN)
+
1^⎤
V_TH(MIN)
⎥
⎦⎥
f
( ) ^P_SYNC
=
V_IN
– V_OUT
V_IN
⎛⎝⎜
I_MAX
N
⎞⎠⎟
2
1+ δ
R_DS(ON)
where N is the number of output stages, δ is the tempera-
ture dependency of R_DS(ON), R_DR is the effective top driver
resistance (approximately 2Ω at V_GS = V_MILLER), V_IN is the
drain potential and the change in drain potential in the
particular application. V_TH(MIN) is the data sheet specified
typical gate threshold voltage specified in the power
MOSFET data sheet. C_MILLER is the calculated capacitance
using the gate charge curve from the MOSFET data sheet
and the technique described above.
Both MOSFETs have I²R losses while the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V_IN < 12V, the
high current efficiency generally improves with larger
MOSFETs, while for V_IN > 12V, the transition losses
rapidly increase to the point that the use of a higher
R_DS(ON) device with lower C_RSS actually provides higher
efficiency. The synchronous MOSFET losses are greatest
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized R_DS(ON) vs temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
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