LTC3738 Datasheet, PDF (25/32 Pages) Linear Technology – 3-Phase Buck Controller for Intel VRM9/VRM10 with Active Voltage Positioning

LTC3738
APPLICATIO S I FOR ATIO
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If C_LOAD is greater
than 2% of C_OUT , the switch rise time should be controlled
so that the load rise time is limited to approximately
1000 • R_SENSE • C_LOAD. Thus a 250µF capacitor and a 2mΩ
R_SENSE resistor would require a 500µs rise time, limiting
the charging current to about 1A.
Design Example (Using Three Phases)
As a design example, assume V_IN = 12V(nominal), V_IN =
20V(max), V_OUT = 1.3V, I_MAX = 45A, f = 400kHz and the
AVP slope is 1mV/A. The inductance value is chosen first
based upon a 30% ripple current assumption. The highest
value of ripple current in each output stage occurs at the
maximum input voltage.
L
=
V_OUT
f₍∆I₎
⎛
⎝⎜
1−
V_OUT
V_IN
⎞
⎠⎟
=
1.3V
(^400kHz)(^30%)(^15A)
⎛⎝⎜_1−
1.3V
20V
⎞⎠⎟
≥ 0.68µH
Using L = 0.6µH, a commonly available value results in
34% ripple current. The worst-case output ripple for the
three stages operating in parallel will be less than 11% of
the peak output current.
R_SENSE1, R_SENSE2 and R_SENSE3 can be calculated by using
a conservative maximum sense current threshold of 65mV
and taking into account half of the ripple current:
R_SENSE
=
65mV
15A^{⎛⎝⎜}1+ ^{342%⎞⎠⎟}
= 0.0037Ω
Use a commonly available 0.003Ω sense resistor.
Take R_AVP as recommended value 100Ω, the R_PREAVP is:
R_PREAVP
=
0.003Ω ^100Ω
1mV/A
=
300Ω
Next verify the minimum on-time is not violated. The
minimum on-time occurs at maximum V_CC:
t_ON(MIN)
=
V_OUT
( ) ^V_IN(MAX) ^f
=
1.3V
20V₍400kHz₎
=
162ns
The output voltage will be set by the VID code according
to Table 1.
The power dissipation on the topside MOSFET can be
estimated. Using a Siliconix Si7390DP for example, R_DS(ON)
= 13.5mΩ, C_MILLER = 2.1nC/15V = 140pF. At maximum
input voltage with T(estimated) = 50°C:
[ ] ^PMAIN
≈
1.3V
20V
(¹⁵)²
1+
(^0.005)(^50°C
−
25°C₎
0.0135Ω
+
(²⁰)²
⎛
⎝⎜
45A ^⎞
(²)(³)⎠⎟
(^2Ω)(^140pF)
⎛⎝⎜
5V
1
– 1.8V
+
1
1.8V
⎞⎠⎟ _(400kHz)
=
0.51W
using a Siliconix Si7356DP as bottom side MOSFET.
The worst-case power dissipation by the synchronous
MOSFET under normal operating conditions at elevated
ambient temperature and estimated 50°C junction tem-
perature rise is:
P_SYNC
=
20V − 1.3V
20V
(^15A)²(^1.25)(^0.004Ω)
=
1.05W
A short circuit to ground will result in a folded back current
of:
I_SC
≈
25mV
(^{2 + 3})^mΩ
+
1^⎛
2 _⎝⎜
150ns₍20V₎⎞
0.6µH _⎠⎟
=
7.5A
with a typical value of R_DS(ON) and d = (0.005/°C)(50°C) =
0.25. The resulting power dissipated in the bottom MOSFET
is:
P_SYNC = (7.5A)²(1.25)(0.004Ω) ≈ 0.28W
which is less than one third of the normal, full load
conditions. Incidentally, since the load no longer dissi-
pates any power, total system power is decreased by over
90%. Therefore, the system actually cools significantly
during a shorted condition!
3738f
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